C02 Pocket SBC completed!

[BigDumbDinosaur]

I meant to ask but forgot. What did you use to program the Atmel GAL? It seems many programmers won't work with Atmel's devices.

[BillO]

BigDumbDinosaur wrote:

I meant to ask but forgot. What did you use to program the Atmel GAL? It seems many programmers won't work with Atmel's devices.

While I'm not the person you asked, I have a cheap and cheerful Genius 540 that will program an ATF22V10C. It will do some 19 or so Atmel GALs.

[floobydust]

telbee71 wrote:

That PCB is a work of art! Excellent project.

Thanks for the kudos... it did take a bit of time to fit it within the MiniBoard parameters/limits, but I'm happy with the end result. I have 3 boards running for 6+ months now. So far, they've been flawless.

BigDumbDinosaur wrote:

I meant to ask but forgot. What did you use to program the Atmel GAL? It seems many programmers won't work with Atmel's devices.

I picked up a Dataman 40-Pro about 5 years ago... not a cheap programmer, but it's pretty flawless when programming all of their supported devices (which is a very long list) and the software is updated regularly. The software also has some very good features, i.e., generates checksums, buffer editing, etc. and is simple to use. Overall I've been very happy with it.

[BillO]

This is a cool looking project. Nice clean layout. I like the fact that you've created a great monitor for it. Nice work.

What are the dimensions of the board?

Would you be able to produce a JPEG of the schematic?

[floobydust]

BillO wrote:

This is a cool looking project. Nice clean layout. I like the fact that you've created a great monitor for it. Nice work.

What are the dimensions of the board?

Would you be able to produce a JPEG of the schematic?

Thank you Sir... it was a fun project, now working on porting EhBasic to it and integrating it with my C02 BIOS/Monitor, which needs an upload function added for Xmodem. I used Express PCB's Miniboard 4-layer service, so the dimensions are 3.8" x 2.5". The zip files contains everything one would need to build one, and/or modify it. I went into ExpressPCB's schematic app and exported to a BMP, then converted to a JPEG and attached it here. It's a fairly simple circuit

Note that the final board is using the newer low power version of the AT22V10CQZ and the main clock oscillator is at 6MHz, not 4MHz as shown. The SCC2691 is basically limited to a 6MHz CPU clock rate, albeit I have one DIP version that survives an 8MHz clock.

[BillO]

floobydust wrote:

It's a fairly simple circuit

The best kind.

Thanks for the schematic - I don't have Express PCB software.

[BigDumbDinosaur]

floobydust wrote:

Note that the final board is using the newer low power version of the AT22V10CQZ...

According to the Microchip (Atmel) data sheet, Voh minimum for the GAL is 2.4, which is below what would be considered a solid CMOS logic 1. Interesting...

[BillO]

BigDumbDinosaur wrote:

floobydust wrote:

Note that the final board is using the newer low power version of the AT22V10CQZ...

According to the Microchip (Atmel) data sheet, Voh minimum for the GAL is 2.4, which is below what would be considered a solid CMOS logic 1. Interesting...

It's a worst (nigh impossible) case scenario. The spec of 2.4V is a minimum guarantee when sourcing 4mA with Vcc at it's minimum. It's not for normal conditions. Look at the graph (page 10 on my datasheet) [labeled ATMEL ATF22V10CZ/CQZ OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)] It clearly shows the actual output voltage vs. output current under normal conditions and is typical for a CMOS device utilizing the ubiquitous MOSFET totem-pole output. In the case of this SBC project (and I daresay most of the projects we would likely be building) the actual load will be in the low uA range and the output voltage will be pretty close to 5V.

How would you even get 4mA load? TTL Iih is about 40uA @ 2.4V. 4Ma would be equivalent to driving more than 100 TTL loads or 4000 HC/AC loads.

I think we need to take some of these specs with a grain of salt, or at least a look at the entire story. GALs, DRAM, SRAM, EEPROM and EPROM chips of all sorts sport this 2.4V Voh spec, but are/were used all the time in CMOS environments. Not just by us 'amateurs' either, but also by designers of commercial and industrial equipment.

[floobydust]

BillO wrote:

BigDumbDinosaur wrote:

floobydust wrote:

Note that the final board is using the newer low power version of the AT22V10CQZ...

According to the Microchip (Atmel) data sheet, Voh minimum for the GAL is 2.4, which is below what would be considered a solid CMOS logic 1. Interesting...

It's a worst (nigh impossible) case scenario. The spec of 2.4V is a minimum guarantee when sourcing 4mA with Vcc at it's minimum. It's not for normal conditions. Look at the graph (page 10 on my datasheet) [labeled ATMEL ATF22V10CZ/CQZ OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)] It clearly shows the actual output voltage vs. output current under normal conditions and is typical for a CMOS device utilizing the ubiquitous MOSFET totem-pole output. In the case of this SBC project (and I daresay most of the projects we would likely be building) the actual load will be in the low uA range and the output voltage will be pretty close to 5V.

How would you even get 4mA load? TTL Iih is about 40uA @ 2.4V. 4Ma would be equivalent to driving more than 100 TTL loads or 4000 HC/AC loads.

I think we need to take some of these specs with a grain of salt, or at least a look at the entire story. GALs, DRAM, SRAM, EEPROM and EPROM chips of all sorts sport this 2.4V Voh spec, but are/were used all the time in CMOS environments. Not just by use 'amateurs' either, but also by designers of commercial and industrial equipment.

I was basically typing a similar post to Bill's, but he beat me to the submit.... and as noted, the datasheets for the SRAM, EEPROM and the 2691 UART all have this same 2.4V spec, albeit at slightly different currents. In my usage of the 22V10, all outputs are active low so I would not expect any significant loading for driving any device line inactive. While doing some initial scoping on the finished board, I'm pretty sure the output pins on the 22V10 were close to 5V when the device was inactive.

[BigDumbDinosaur]

BillO wrote:

It's a worst (nigh impossible) case scenario. The spec of 2.4V is a minimum guarantee when sourcing 4mA with Vcc at it's minimum. It's not for normal conditions. Look at the graph (page 10 on my datasheet) [labeled ATMEL ATF22V10CZ/CQZ OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE (VCC = 5V, TA = 25°C)]...

For the benefit of others, here's the graph to which Bill is referring:

GAL22V10 Voh vs. Ioh

Note that the GAL's Voh doesn't get anywhere CMOS logic 1 territory until Ioh is vanishingly small. While a CMOS input draws virtually no current when the circuit driving it is quiescent, the GAL has to contend with transitory loading by the circuit's parasitic capacitance. Although the above graph indicates that the 22V10 will produce 3.50+ volts as the load approaches the microampere range, much more current will be demanded while the parasitic capacitance is being charged to Voh. Unavoidably, signal edges will be rounded to some extent, creating the potential for unreliability at higher clock speeds. The result is the Fmax for any given circuit could be much less than what timing calculations suggest it should be.

Incidentally, the 65C816's data sheet indicates that Vih must be at least VDD × 0.8 to be recognized as a logic 1. That's 0.5 volts higher than the theoretical Voh of the 22V10 when loaded at the microampere level. On paper, it shouldn't work, an observation that gets back to a past topic concerning the true nature of the 65C02's and 65C816's inputs (TTL or CMOS).

[BillO]

I beg to differ BDD. That diagram is not accurate nor precise enough to see what is happening at the low uA range (~1-25uA) which is what we'd typically see in our little systems. I mentioned that diagram only to note that the spec of 2.4V is for unusual conditions. Vcc at minimum and Ioh at 4mA.

I'd be willing to bet the price of a shiny new W65C02 that if you loaded one of these GALs with 50K resistor (~20ua) you would see better than 4V at the output. I'd go further to let you test 1000 of them to see if you could find one that did not deliver better than 4V.

Honestly, I do understand the physics behind these devices and know how they work, my being a physicist and all.

It is interesting to note too, that you have in your own POC V2.1 several devices including an EPROM and an ATF1504AS CPLD that list that very same 2.4V Voh. The EPROM is actually at a much lower current too.

Both the enhanced Apple //e and 11gs used WDC CMOS CPUs and both employed DRAM and ROM chips that specified 2.4V Voh. It is a matter of record that 10s of thousands of those computers worked fine.

Also, the RCA COSMAC VIP utilized a CDP1802 cpu, which specified a Vih @ > 4.5V, yet employed 2114s for RAM memory, which specified .... Voh = 2.4V @ 1mA. Yet that system worked fine too.

Did the engineers at Apple and RCA get it wrong, or did they understand that specification really means even if things get really bad (Vcc=4.75V and a load in the mA region) the thing will still deliver at least TTL levels?

In any case, this is probably not worth our arguing about.

EDIT: Changed one 'and' to 'at', one 'a' to 'at' and 'are' to 'our' - so that normal folk can understand...

[Dr Jefyll]

Quote:

Incidentally, the 65C816's data sheet indicates that Vih must be at least VDD × 0.8 to be recognized as a logic 1.

I see BillO has posted while I was typing, so I'll keep this short. Yes the data sheet cites VDD x 0.8 as the minimum, but it does not say a below-minimum value will fail to be recognized as a logic 1. I think (as Garth said somewhere) that the minimum VIH and maximum VIL figures for an input simply establish the conditions under which the part is rated re: the various propagation times. The timing spec's are a guarantee, and this is the fine print. They're saying, give us these input voltages or else we have no obligation to meet the speed guarantee (ie, the thing will probably be slower).

[GARTHWILSON]

Farads = amps x seconds / volts

To charge 10pF up 4V in 5ns requires 8mA average over the 5ns.

Charging 10pF from .4V to 2.4V (ie, a 2V transition, half the 4V above) in 5ns requires 4mA average over the 5ns.

We probably want the transition to be even faster then 5ns though, since goals of around 5ns include the propagation delay of the gate(s) as well. This further increases the current requirement.

[BigDumbDinosaur]

BillO wrote:

I'd be willing to bet the price of a shiny new W65C02 that if you loaded one of these GALs with 50K resistor (~20ua) you would see better than 4V at the output. I'd go further to let you test 1000 of them to see if you could find one that did not deliver better than 4V.

Oh, I don't doubt that at all. However, as Garth notes above, the current draw during an output's transition from low to high will be much greater than 20µA, which load will pull down the output voltage until parasitic capacitance has been sufficiently charged. That has the effect of rounding the edges and if sufficiently severe, provoking problems.

Dr Jefyll wrote:

Yes the data sheet cites VDD x 0.8 as the minimum, but it does not say a below-minimum value will fail to be recognized as a logic 1...[WDC is] saying, give us these input voltages or else we have no obligation to meet the speed guarantee (ie, the thing will probably be slower).

The problem, of course, is we don't know just how much those "sub-normal" input voltages affect the MPU's performance. All we know is that despite the "official" Vih minimum rating of VDD × 0.8, the MPU seems to function okay with what are TTL outputs from other devices in the system.

BillO wrote:

It is interesting to note too, that you have in your own POC V2.1 several devices including an EPROM and an ATF1504AS CPLD that list that very same 2.4V Voh. The EPROM is actually at a much lower current too.

POC V2.1 is unstable above about 5 MHz. Contrast that with POC V1.1, which is stable at 15 MHz sans the SCSI host adapter and solid at 12.5 MHz with the host adapter installed. V1.1 uses the same EPROM as V2.x, as well as an SRAM that has Voh ratings equal to the SRAM in the V2.x units.

So, what is the difference?

POC V1.1 uses 74AC discrete logic, which drives its outputs close to Vcc and Gnd, even at the full-load rating of 24mA. Hence the 65C816's control inputs are driven with a very short rise or fall time, since the logic can produce enough current flow to rapidly charge/discharge parasitic capacitance. The ATF1504AS can't do that and while it can produce nearly 4 volts Voh with the typical CMOS loading (determined by actual measurement), it can't produce that voltage at the beginning of a circuit state change, due to the charging load of the parasitic capacitance.

I should add that both POC V2.0 and V2.1 exhibit essentially identical symptoms when an attempt is made to elevate the Ø2 rate. The principal difference between the two designs is V2.0 has a single QUART and V2.1 has two DUARTs. They both use the same RAM, ROM and CPLD. CPLD code is slightly different between the two, since 2.1 needs an extra chip select for the second DUART. However, the intermediate logic statements in both versions are the same.

I believe the common denominator in this situation may be the Voh rating of the CPLD when under any significant loading. However, it's not something I've been able to conclusively prove.

[BillO]

BigDumbDinosaur wrote:

Oh, I don't doubt that at all. However, as Garth notes above, the current draw during an output's transition from low to high will be much greater than 20µA, which load will pull down the output voltage until parasitic capacitance has been sufficiently charged. That has the effect of rounding the edges and if sufficiently severe, provoking problems.

That is true, but it's not nearly as bad as you might think from looking at a spec sheet. The internal resistance of the output MOSFETs is not a constant over time. It is unfortunate, but manufacturer's spec sheets leave out what I consider to be very important information about the behavior of their devices. For instance the Voh characteristic we are talking about is a DC characteristic and not very revealing about the dynamic behavior.

The below traces are the /OE signal in my recent project at 16MHz. This signal drives both the RAM and the ROM /OE and the line, with chips inserted, and scope probe attached measures at 55pF and 257K ohms, both measurements taken at 10KHz. We can see the following:

1) Rise time (which is not very significant for a /OE signal) to 2.4V = 2.3ns
2) Rise time to 4.0V = 4.7ns

and, most significantly

3) Fall time from 4.46V to 0V is only 3.4ns

(not sure why the actual measurements don't get put in the trace image files - a bug in the scope software?)

1) and 2) demonstrate an important characteristic of MOSFETS. That once turned fully on, (~1ns in this case - see where the rising edge turns most vertical) they can and will pass significant current until thermal effects begin to take hold and increase their resistance. Using the formula Garth gave us, we can see the initial current (0V-2.4V) averages at ~57mA and that the average current to drive the line all the way to 4V is ~47mA. Considerably higher than the 3.2mA suggested by the data sheet of this Lattice GAL20V8C which, as usual, gives us less information than we really need to determine if a device will actually suit our needs.

3) Shows that in this rather typical situation, the GAL will indeed produce a valid CMOS Vih of 4.46V. Not only that, but it will assert the /OE signal from that 4.46V all the way to 0V in just 3.4ns - an average current sink of ~72mA.

Now, after having said all that, the scope probe itself adds a measured 16pF load to the line, so the actual performance will be better than depicted here.

1)

2)

3)