Chromatix wrote:
If the cycle counting in my own emulator is correct, at 4MHz my assembly implementation should beat the Amiga 2000 entries in the table! That's a CPU with hardware divide instructions and, presumably, a much higher clock speed. Makes me wonder what some of those compilers are up to.
Code:
macbook-pro:lib6502++ chromi$ ./test6502 primegap.bin 4000 4498 | fgrep RTS
4122: RTS ; 340071 cyc
4122: RTS ; 945137 cyc
4122: RTS ; 11181386 cyc
4497: RTS ; 42165323 cyc
4497: RTS ; 113473325 cyc
4497: RTS ; 3767409738 cyc
In this case I can simply divide your cycle counts by 1,000,000 and get the execution time in seconds for a 1 MHz CPU - that would make comparisons to other results easier. Did you using 65
C02 instructions? Perhaps you can add a source file - a listing might be too long?
The 68000 has a different clock scheme than the 6502. A cycle took 4 clocks (IIRC the TAS instruction took 6). I don't look at the clock speed anymore - it isn't helpful. I think it is better to ask for the
required memory spped (access time). Using the required memory speed (e.g. 500ns for a 1 MHz 6502 system) you can compare various clock architectures easily. The Z-80 took 4 cycles minimum (6 for opcode fetch), the TMS 9900 requires 3 cycles (with 4 non overlapping phases
![Shocked :shock:](./images/smilies/icon_eek.gif)
), a RCA1802 uses 4 clocks for each memory cycle. Running a TMS-9900 @ 3 MHz requires roughly 600ns RAMs, similar to a MC-68K with 4 MHz. With an equal memory speed requirement as a calculation base you may then compare different CPUs fairly. So 1 MHz for 6502 corresponds to 3 MHz for TMS9900, 4 MHz for RCA1802 or MC68000. I have no databook at hand for the Z-80, but I assume a 500ns RAM would work for clockspeeds around 3.3 MHz (perhaps 3.0 MHz only).
Cheers,
Arne