For others' benefit, the new(ish) page on it is at http://wilsonminesco.com/BenchCPU/ .

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

What a reading, I will try to translate it to spanish for my father, he'll be impressed.

I bought yesterday a pair of R65C51P2 on ebay, I would had prefer a 4Mhz part but couldn't find it at good price, anyway it's more than enough to start with. By the way I bought also a couple of R6522AP, I know it is NMOS but also cheap for testing

I have a question about the NMI line of my WDC 65C02, it had been working well until past weekend, but now I can't pull up it to 5V, I have 3k3 pull up resistor on both IRQ and NMI lines, IRQ is working fine, but if you measure voltage on NMI pin it returns around 1.5V.

I had try with a 1K resistor and then it goes up to about 2.5V, seems that it is somehow damaged.

However, measuring the resistance on IRQ and NMI returns the same reading.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I don't think so because I have leave NMI line with only the 3k3 pull-up resistor and I'm measuring voltage on this and getting around 1.5V when in that case it should return about 5V

Interrupt is not working obviously because in this state it is always low and there isn't any edge change if you pull down it to 0V

Anyway it is only for curiosity, I will use the 4Mhz Rockwell for the new upgraded computer



Thank you for that, I didn't know it, I suppose it means that the 6522 inputs pulls itself up and then I need an active pull-down/pull-up signal if I want to use it as an input, is that correct?

Yes. Left unconnected, they will act like they were pulled up; but pulling down requires a strong, low-impedance signal source. I got bit by this when I didn't know it yet and I had a very high-impedance signal source, and it couldn't pull them down.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Hi,

I've been thinking and designing the schema of the new board to upgrade the computer and I'm waiting now to the new parts to arrive.

It will be on top of my current board and I had decided to maintain the ATMega instead of the new parallel flash, the reason: while thinking in how to develop and test the software needed to run the new system I didn't like that the use of the flash would be annoying because I will have to take it out of the socket to program it.

I was looking for a solution and then realized that I already have it! Since I already have the ATMega I will use it in a similar way I do now to load the software into RAM from their own flash, through a simple bootstrap code as I am doing now.

At first the ATMega will act as both EEPROM and take control of the phi0 clock and buses to feed the 65C02 with the bootstrap code. The difference with my current design is that in the new system when the bootstrap completes the ATMega will only be driving phi0 using one of its PWM outputs and nothing more, leaving the 65C02 running on its own with the new ACIA and VIA's.

I think the use of the ATMega will leave me this advantages:

- ROM-less system

- Easy 65C02 main software update using ISP to upload it to the ATMega

- Easy main clock frequency change, again only programming ATMega using ISP port to change the timer pwm output frequency (from few Hz to 8Mhz)

As now I won't have ROM I decided to use Daryl SBC-2.5 address decoding schema to maximize the available RAM, then I will have:

0x0000-0x7EFF RAM
0x7F00-0x7F7F I/O (up to 8 ACIA/VIA)
0x7F80-0x7FFF unused
0x8000-0xFFFF RAM

I have modified the original address decoding a little to add a new input from the ATMega that will control through a NAND gate the I/O and RAM CS during the system boot.

For the moment I will put two ACIA (one for main user I/O and the other one to use it as UART bridge with other serial devices) and two VIA.

I will also add a I2C-6 and 65SIB ports (will have a lot of fun trying to do it with the VIA's) and some DIP switches to enable/disable IRQ/NMI outputs from the ACIA's and VIA's, enable/disable chip selects, etc.

As I had left an expansion port the mods that I have to make to my current board are minimal, only some wires, I have completed the software of the ATMega and tested a simple address decoding, I will upload new photos when the parts arrive and the ACIA work.

I use home built and other 6502 systems in my lab all the time. I usually build the interfaces I need on a breadboard or prototyping board and use a combination of ML routines and BASIC to run the experiments. My methods have been a bit messy and right now I'm working on a couple of projects to make the whole process a bit tidier (and faster) by using custom PCBs for most of my interfaces and using a new 6502 system with a short (3 slot) bus to be able to reconfigure the systems quickly, neatly and reliably as needed.

65C51s from Rockwell, CMD, RCA, etc... are available in eBay for chump change. Or I have about 50 of them lying around if you cant find them. You can have as many as you want for $4 each + postage. Just let me know. Th bug in the W65C51S is easily dealt with in firmware. It's really the only choice if you want to run faster than about 4 or 5 mHz. I know the older 65C51s are only rated for 2mHz systems, but I find many can run much faster, but certainly not at 14 mHz.

I'm a great fan of using PLDs like GALs or the newer Atmel equivalents. The nice fast Lattice items (7.5nS) are easily and cheaply found on eBay. I use a cheap ($50) programmer that works like a charm for both my PLDs and EPROMs. Can't really play this game without a programmer!

_________________
Bill

Hi,

The 65c51 arrived yesterday and it is running fine!

For the moment, as I don't have some glue logic IC's yet (74HC30 and 74HC138) to do Daryl's SBC 2.5 address decoding and now I am only using one I/O IC I am using the one that Garth shows in his primer, modified for my system:



I have tried it up to 4Mhz and it works well, despite the mess of long wires I have and that the 65c51 it's a 2Mhz part.

The bootstrap code I'm using is that simple:



The ATMega have virtually mapped this code into their flash in $8000 and Daryl's SBC monitor into $E800, during the boot process the atmega drive phi2 manually and controls the glue logic so all the read from bootstrap and ROM ranges are made to it, and all the writes to $E800-$FFFF are made to RAM, all the rest are ignored and the 65C02 is feeded with NOP if it issues a read from any other memory range.

Once the boot is complete the ATMega enable permanently his glue logic output and puts his OC1A output (it is the phi0 input of 65C02) into CTC mode at 4Mhz frequency and enter in a endless loop doing nothing.

By the way I have upgraded the reset circuit with a DS1813.

I'm very happy that although I had not this updates in mind when I built the sbc it adapted very well without doing changes to the original board, I'm waiting impatiently for the rest of the pieces to continue.

Hi,

Finally the new PCB has arrived! It connects to the existing board using some pin headers

The new expansion board have these:

- Up to three 65C22, stacked, the last one don't have the i/o ports populated on the PCB, so I have to put it on their own perfboard

- Up to two 65C51, stacked too, one for main com through the FTDI, but it have all the i/o pins populated so can use it for whatever I need

- It have pin headers to use jumpers for all the IC interrupts (to use both with IRQ or NMI) and IC select

- Switch to select main power source: from the FTDI or external micro-USB/screw connector (this one have an AMS1117-5.0 to use >5.0V source)

I used an ATtiny85 to generate the clock for the ACIA and I put a jumper on the PCB to select 1.8432Mhz or 3.6864Mhz, so I can use it up to 230400bps using 16x

The ATtiny85 also generates a 100Hz signal on an other output pin so I can use it as a jiffy clock, also with a jumper to the 65C02 NMI to select it or not.

As you can see in the photos I have stacked the 65C22 and 65C51 to save space, also put the capacitors and resistors under them.

The glue logic it's more or less the same that Daryl uses in their SBC-2, only with some mods for my boot scheme using the ATMega, all the system run in RAM and the I/O uses only 256 bytes of address space.

At one edge of the board I put pads for the address and data bus, interrupts, phi2, r/w and all the signals needed if I want to expand it a bit more, and all the other pads you see are for use it as a perfboard to put custom common use circuits as i2c or spi.

It is working perfectly at 4Mhz using 4Mhz Rockwell parts and one WDC W65C22S

Good summer!

Interesting stack technique. When I thinking about stacking two 6522 I always think OH NO! because of the heat - but that was back then when these parts are NMOS only.

And your colored headers - really neat.

Thanks for these photos.

I don't quite understand the stacking. How are you segregating the signals to the chips? Typically, when things are stacked, you see little jumper wires and what not to distinguish the few pins, but I don't see anything like that here.

The upper 6522 is mounted on a tiny daughterboard, on which the socket appears to be slightly offset from the header it's standing on.

Oh, I see.

On the first picture we see the space for the chip, and then the extra pin rows next to them.

The daughter card plugs in to those extra holes, and mounts the chip.

Hi,

Sorry, I forgot to take some pictures

Yes, I simply soldered female headers on the pcb 0.1 inch wider and made a simple perfboard with the socket for the 6522 and pin headers to connect to it.

I pushed the male pins all the way so I can solder both the socket and pins on the same side of the perfboard and gain height to save the other IC.

Here are some pictures