Maximum bang for minimum buck is THE overriding factor for any CPU instruction set. Remember that when the 6502 came out, memory was faster than CPUs were, so it made sense to move as much program state into RAM as possible. Hence, zero-page.
Now-a-days, it's just the opposite; it's easier to have CPU registers instead of something complex like zero-page. As a result, your instructions can be made simpler. RISC processors epitomize this, where the 3 operands are register ID fields ONLY. No addressing modes at all -- just registers. And, quite often, you even lack word-width specification. ADD will produce a 32-bit sum (assuming a 32-bit CPU), regardless of whether you used an 8-bit, 16-bit, or 32-bit load instruction to fill the registers.
Which brings us to the issue of addressing modes on the load and store instructions. Minimize them as much as possible. Ideally, one, and only one, addressing mode would be provided. However, practical matters often suggest two, sometimes three. Either way, definitely a far cry from the 65816's 24 gob-smackingly complex addressing modes.
The ultimate form of this is MISC -- Minimal Instruction Set Computers. These are typically 0-operand instruction sets. As such, they rely on a data stack to manage parameters. Since instructions require no operands (since they're always implied as the topmost n items on the data stack), the instruction encoding can be much smaller. 5 bit opcodes on MISC processors is not unheard of. In a 16-bit word, this means you could pack 3 MISC instructions per 16-bit word. Hence, one opcode fetch grabs 3 instructions. Over a 65816-like bus, expanded to 16 bits, this means you have one cycle for opcode fetch, and up to 3 cycles for load/stores. Therefore, cycle times are predictable at 1.3 cycles per instruction. Again, this is assuming the simplest possible processor implementation. And, yet, it still makes the 6502/65816's performance pale in comparison.
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