Bill Mensch did a good job on the instruction set, but his mask leaves a lot to be desired since it does not lend itself to high speed operation. Unless they've fixed things, on the 8 mhz parts REP and SEP take 250 ns to operate so you have to put a NOP after each one OR you have to stretch the clock the way the transwarp does. WDC has admitted that this is caused by very long signal lines.

Did you know that W.D.Mensch worked for the company that originally designed the 6502? I think that qualifies him to do design work in his kitchen after a decade of experience.

I'm not arguing with that, in fact it's one reason I admire his architectural enhancements in the 65816. All I'm saying is that his timing margins are lousy because of it. I am actually building stuff that uses his chips so I have to know about this. The project I am building now will require wait states on the DRAM, not because the DRAM is too slow, but because the WDC chip's timing margins are very bad. (For a 4 mhz WDC chip you need 8 mhz'able parts, and WDC's timing margins are forcing me to (a) make my timing generator a lot more complex or (b) add a wait state. I decided to make the best of it and perform a hidden refresh during the wait state.)
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What they did is produce a mask that works but has been giving them gobs of trouble when they try to shrink it. I will stop ragging on them IF they can get into production a part that:

• runs at 15 Mhz (14.31818 or better, really) w/ 35 ns SRAMs
  
• is available in single quantities _somewhere_ for reasonable $$$
  
• does not have the blasted REP/SEP timing problem
  
• handles ABORT in a usable way (it doesn't currently)

What I am ragging on is the fact that they are trying to milk more speed out of the same mask when it would be a lot easier to redesign the mask itself so it is native to a newer technology that does run at higher speeds.

ASIC reverse-engineered the chip from WDC's timing diagrams. Their utmost goal is "105% compatibility" meaning that all software will work (even the Disk ][) and that the REP/SEP quirks will be gone. They might have fixed ABORT, but I don't know for sure.
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Gate arrays are now fast enough (and big enough for an 8000 gate design like the 65816); they are also cheaper to make and are very easy to second source... in other words, Apple loves them. If the ASIC chip really is 100% compatible then Apple will jump on it. (They'd better...)

BTW, Apple has had the tools to do what ASIC is doing for a few years now.

ASIC has claimed from the start that they will be fully compatible with the PLCC version of WDC's chip. This means they will have to at least respect the timing margins given by WDC. From my examination of WDC data sheets I do not think that will be very hard to do.

AE released the TransWarp GS in winter of 1988. The board came stock at 7MHz and 8k cache. They later upgraded the board to 8MHz and offered a 32k cache board. The limiting factor to speed at the time was the "buggy" 816 CPU die. Later Western Design Center (WDC) worked with Sanyo to redesign the die, and the CPU speeds easily reached 10MHz. By this time however AE was out of business.

Well, that's an interesting finding!

Ooo, Modula-2 .. downloaded the full issue to browse later.