GaBuZoMeu wrote:
Now that you can trim your timing relative to PHI2 I could not see a reason why this shouldn't work - except there is some other bus participant still active?
Okey, a poor choice of words from my side. In this particular situation, the use of PHI2 (and change of timing) did not seem to solve the problem at hand. So my guess is that its not related to timing; at least we can move that a couple of notches down the (debugging) priority list.
GaBuZoMeu wrote:
Thinking about this - can you run a loop where the 6502 is reading simply incremented data from your CPLD and place it in some (working) buffer. Perhaps one could get an idea of what is going wrong when seeing what is read. Perhaps there are patterns visible or a tendency for zeros or ones or or or ?
Perhaps you can perform this with regular (PHI2+40ns) and extended (PHI2+240ns) timing as well?
If I go two steps back; the original implementation (without PHI2) was running a program in the CPLD memory, so all the reading was working ok. It was the writing that seemed to have glitches (if the reading was glitchy, the program would have just crashed).
Now, it seems like the reading is glitchy. The program doesn't run at all unless its in a SRAM IC, and looking at the data in the CLPD from a real-time analyzer, its obvious that the CPLD pushes the correct data onto the 6502 bus, but for some reason the 6502 does not get it. The TXB0108 level shifter is between the CPLD and the 6502, so I will have to debug or change that somehow (I don't have the equipment needed here, but I will go to the local Makerspace tonight and see if I can set up things there). I will also test the extended PHI2 timing there (and maybe gather some interesting data in the process).