Hi

I am making an expansion to an older 6502 system that responds to its 6502 address/data bus. One part shows up as expansion memory (for the 6502), another just reads the bus and decodes it. I can get it to work, but I am having timing issues if I change from one machine to another.

The system in general:

NMOS6502<--->Level shifter<--->3.3V CMOS CPLD

The level shifter I am currently using is TXB0108 (8-Bit Bidirectional Voltage-Level Translator with Auto-Direction Sensing and ±15-kVESDProtection).

The obvious problem is the slow transitions from the NMOS side. It shows up as confusion on the buses in between transitions. I have been able to filter this out and get the data and address from the 6502 stable.

The other way around is not so stable and seems to be very time critical (e.g. reading of data from the CMOS side to the NMOS 6502). If I send data 10ns too soon or 10ns too late, I get errors. If I end the data (e.g. put output into high impedance) too soon, I also get errors. Obviously I have to end and put the databus into high impedance on the CMOS side before next cycle (which could be a write), so I cannot wait too long either, but it has more slack than the start.

The real problem is that if I move from one system to another, and the +/-10ns window seems to shift. E.g. I can make it work flawless on one system, but not on two.. A dynamic way to test and adjust for timing sounds too complicated.

Is this normal for the NMOS 6502 or is it just the age (>30 year old components)? Anyone know of a way to get around this?

I have also thought about changing the TXB0108 to a SN74LVC8T245 (non-automatic), but I don't know if that solves anything.

Suggestions?

I would consider a different level shifter: the bidirectional one isn't going to have an equivalent of tristate, I wouldn't think, so there's a danger it will be driving when it shouldn't. Do you have a high speed clock available on the CPLD side and is that how you are shifting your data window? I have a vague recollection that hoglet has to do that on one of his designs, possibly an in-socket CPU replacement project - and that he needs different settings for different hosts. But I think that comes down to the level shifter, again.

By this do you mean you can't gain access to Phi2 clock signal? Phi2 would certainly solve the problem, I'd say.

It might not be that hard if the computers to which you plan on connecting all have the same nominal frequency (example: 1 MHz). You'd only have to design to accommodate errors of a few percent.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
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Perhaps you can feed us with some more information

How is the AB / DB load of the NMOS CPU without your planned extension?
What is the clock speed?
RAMs ROMs so far have an access time of ___?

A 3V3 CPLD should work with series resistors for its inputs driven by NMOS or LS-TTL without harm. Driving (CPLD => NMOS) may require a LS driver (pullups and diodes may be too heavy loads on the NMOS side). 3V3 on the input of a LS gate is sufficient to be recognized as "1".

I wonder why the timing is that critical, what is the speed of the new components? Perhaps they act too fast.

To begin turning on the static-protection diodes in the CPLD, you would need somewhere around 3.5V, and I'm not sure the NMOS 6502 can pull up that high. I'm sure it cannot pull up that high with enough current to threaten those diodes' health. Also, the NMOS 6502 will recognize anything over 2.4V as a logic high, and won't have any trouble with a voltage the CPLD can output. All this is to say I doubt you need the level shifter at all.


For a silicon IC not being run hot, nor being in a harmful environment like the radiation spacecraft have to tolerate, I'm not aware of any damage time will do by itself. For rubber belts and wheels like tape recorders use, sure, they rot. For strings like tuning dials on old radios used, perhaps. For adhesives, sure. Some types of capacitors can deteriorate with age. But not silicon semiconductors, AFAIK.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

There are some time-variant failure modes: crystal defects can grow, and metal can migrate.
Edit: also water (vapour) can penetrate the package to the die.

Well its complicated because any specification seems to be more like a suggestion than actual fact. But I guess a slight adjustment based on some feedback parameter may be the only way.

If you've got a clock there shouldn't be a problem - your circuit is just like any other peripheral. So it's a matter of figuring out what's going on.

If you don't have a clock, that's very different, because somehow you need to infer the clock position from the changes on the signals you can see.

Crystals' frequencies drift with age, but the drift rate slows down with age also. Are you thinking of something else? I'm only aware of the problem of metal migration with high temperatures and currents. We dealt with this where I worked in applications engineering at a VHF/UHF power transistor manufacturer in the mid-1980's. I have not experienced any problems with semiconductors of my own in equipment from even the 1960's, let alone the 1970's or later. As for moisture, many semiconductors are "passivated," meaning they are given a protective coating. I have no idea if the NMOS 6502 got this treatment in wafer fab. I don't know much about that part anyway, as I was in applications engineering, not wafer fab. The engineers in wafer fab would take our test results and get together and discuss changes to dopings, ion implantation, and various processes that were foreign to us who were only in electronics, not chemistry or the physics of making the wafers.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

By crystal defects I mean defects in the crystal from which the chip is cut. A defect may be too small to affect operation at the time of sale but after 30 years may have grown.

I'm sure manufacturers do what they can to make chips with an acceptable lifetime, but I'm saying that there are failure modes, and there is such a thing as life testing. The oldest chips we use will also have had less rigorous treatment (both manufacture and QA) than the chips you buy today - not least because geometries are much finer now, but also because testing is more sophisticated now.

Well, actually I do know a lot about what can happen since I work with Silicon R&D in a cleanroom. Some time ago I did a decapping of an old 6560 which had an early date code. Those were probably more prone to what we call "catastrophic failure" in life-time testing terminology (in which something burns off), but before you get to that failure mode, things can change.

A specific thing with the early 6560 (which was made in the same lab as the 6502) is that it had very thick dielectric (which also act as a passivation/protection). There was also a presentation somewhere that said MOS had problems with too high doping of some layer (might have been poly-Silicon or unintended doping of the dielectric) in the start, but I don't know the details. Analyzing such is (on an old 6502) is not impossible, but expensive and difficult. Anyway, if they had some process that was less than optimal, it would be possible that this could lead to diffusion effects during usage. E.g. wrong doping level can give higher resistance which leads to local heating (usually in contacts), that then leads to metal migration and (eventually) failure. For a hot component this would progress faster, while for a normal (not so hot) component it would take longer time. In todays components one always have diffusion barriers, and although they may have had them in 1980, they were probably not that advanced.

Well, the NMOS seems to be 2MHz, and the ROM access is 450ns. I think the RAM is slightly faster (200ns?).

You are right about the resistors.. and the more I think about those... well, they are probably a really poor choice for driving the old NMOS input. Some of the dedicated outputs can latch in 1ns... ooops.

Hmm.. maybe I should put in some series resistors to ease the driving of the NMOS bus. What comes to mind is ringing of the signal bus. The capacitance of those old lines is certainly not going to live up to expectations when latching that fast...

Anyway, thanks for all the input here. I have a good idea of were to start looking now.

Not to speak for Jeff, but I think he is getting at using Phi-2 to time your activity. For instance when the 6502 is writing R/W is driven low, then when Phi-2 goes high the 6502 address is valid and when Phi-2 goes low the data is valid. When it is reading, R/W is driven high, and again when Phi-2 goes high it's address will be valid and when Phi-2 goes low it expects the data to be valid.

You should be able to use R/W and Phi-2 to determine all interaction with the 6502's DB and AB no matter what clock speed the CPU is running at.

_________________
Bill

(Broadly, Bill, I agree with your description, but do note that the rising edge of Phi2 is not guaranteed to be related to the time when the data and address busses are valid. It's usually late enough for practical purposes, although it's inconveniently late for some.)

Not the data bus on the rising edge - only the address bus. For the NMOS 6502 @ 2MHz the address set-up time (Tads) is quoted as a maximum of 150ns from the fall of Phi-2 - so the address bus should have been valid for at least 100ns before Phi-2 rises:

Tcyc-Tads-TWHphi2=100ns (min)

The data bus must always be valid on the falling edge of Phi-2.

Edit: Perhaps this diagram helps visualize my reasoning:

_________________
Bill