BigDumbDinosaur wrote:
Voh of the AMD 27C256-55 EPROM I'm using is Vcc × 0.7 minimum, which is definitely in CMOS logic 1 territory.
At what current draw? Most of these CMOS chips use similar output circuitry (I'm sure someone will step in to disclaim this) and will provide different Voh at different current draws. This really only makes sense. For instance, the ST Micro M27C1001 specifies Voh = 2.4V @ 400uA
AND Voh = Vcc-0.7V @ 100uA. The 2nd spec is for CMOS environments - like we are talking about. I wonder what the spec for the W2457AK would be at a more reasonable 100uA rather than whopping 4mA?
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Yet in my other project the 15ns GAL limits the speed to below 15MHz. On that one I can get 17MHz with using a 7ns GAL.
Are you using any pins as nodes in the other project? I find it hard to believe that a 15ns GAL can't stay with a 15 MHz clock. Also worth noting is if inputs to the GAL are being driven at TTL levels instead of CMOS levels there may be delay over and above the nominal 15ns rating.
No, no nodes. I can post the CUPL code if you wish. In fact, that restriction goes away if I use !WRB to drive /OE instead of !(Phi2 & RWB), but I did not mention that as it goes against the common wisdom. However, facts are facts - but ... whatever, right?
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As it turns out I have decided to do away with the delay for this project. It works without it and at a speed much higher than I am going to rate the project. I need the extra output pin on the GAL for something more practical.
I was going to suggest implementing wait-stating so you won't have to get bogged down by the performance of the ROM, but I think you'd need an extra pin to use as a node to set up the flop needed to generate the wait-state. That would be in addition to the pin driving RDY on the 'C02. The 16V8 isn't going to cut it.
True - I have run out of real estate. A faster EPROM would be a better solution. BTW, thanks for that link. I ordered 5 of the 55ns devices.