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 Post subject: DEC implied
PostPosted: Fri Jan 19, 2007 5:04 pm 
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Joined: Fri Jul 28, 2006 12:12 am
Posts: 27
Are there some versions of the 6502 that allow DEC as an applied addressing mode?

I have some source code that reads like the following....

lda #$10
dec

But the 6502 Simulator give a
ERROR E024: Addressing mode not allowed.


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 Post subject:
PostPosted: Fri Jan 19, 2007 7:02 pm 
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Joined: Fri Aug 30, 2002 1:09 am
Posts: 3783
Location: Southern California
DEC with no operand, also written as DEA for "DEcrement Accumulator" is op code 3A and is available on all the CMOS versions ever made.

The NMOS ones haven't been made in decades, but CMOS ones are being made even today in huge volumes by licensees of Western Design Center. These have 212 op codes, versus 151 for the NMOS. Some of these are for new instructions, not just added addressing modes for old instructions. The CMOS ones have all the bugs fixed, use a lot less power, can drive heavier loads, have an onboard oscillator, have a schmitt-trigger RST\ input so you can use a simple RC for RST timing, now have pins for bus enable (BE), memory lock (ML\), and vector pull (VP\), the clock can be stopped in either phase, the part can be run over a much wider voltage range with spec.s down to 1.2V, and of course are much faster, being spec'ed for 16MHz although I understand a couple of core licensees have run them at 50 and even 200MHz inside custom ICs.


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 Post subject:
PostPosted: Fri Jan 19, 2007 8:29 pm 
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Joined: Wed Jan 17, 2007 1:04 pm
Posts: 2
Location: Rochester NY
hi
in an old vic-20 instruction set listing i have it lists

DEC decrement memory by one

so the syntax would be

DEC $1000 ; decrement location $1000 by one

HTH , dana :)

ps: just saw there is also

DEC $10 ; zero page
DEC $10,X ; zero page,x
DEC $1000 ; absolute
DEC $1000,X ; absolute,x

in trying to answer this i see how rusty i am , it's been more years than i care to remember :oops:


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 Post subject:
PostPosted: Sat Jan 20, 2007 5:35 am 
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Location: Southern California
copperclad: The VIC-20 had an NMOS processor and was missing a bunch of instructions and addressing modes of the current-production 6502's which do have DEC-accumulator and an INC-accumulator op codes. They also have (and the VIC-20 is missing):
    BRA (Branch Relative Always)
    PHX, PLX, PHY, PLY (push and pull X and Y without disturbing A)
    STZ (store a zero without disturbing the processor registers, with various addressing modes)
    JMP(ind,X)
    BIT immediate, zp,X, and abs,X
    TSB, TRB (test and set bit, test and reset bit, in ZP and abs)
    indirect addressing mode for ORA, AND, EOR, ADC, STA, LDA, CMP, and SBC
    SMB, RMB (set memory bit and reset memory bit, zero page, where the bit number is in the op code itself)
    BBS, BBR (branch on bit set and branch on bit reset, zero page, where the bit number is in the op code itself)
    STP (stop the processor)
    WAI (wait for interrupt)
When you get to the 65816 processor, you'll have even a lot more instructions and addressing modes that open up new possibilities.

kernal34: If you're using an old computer especially like the Commodore 64 which used a 6510 processor which was never made in CMOS, then you'll have to live with its limitations. Otherwise, if you're making your own computer, there is no reason to use NMOS 6502-family processors. Definitely go to CMOS for the advantages I listed above in the earlier post.


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 Post subject:
PostPosted: Sat Jan 20, 2007 10:38 am 
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Joined: Sun Aug 24, 2003 7:17 pm
Posts: 112
DEC alias DECA is a new CMOS instruction to decrement the accumulator. You can for example replace it with:

Code:
CLC
SBC #$00


But then watch up with how the adjacent code use flags! In some programs one could possibly use the replacement:

Code:
PHP
CLC
SBC #$00
PLP


in which case no flags change due to the "DECA" replacement but this might also be wrong! It all depends on the context and the intentions of the programmer!

I recommend you to test the original CMOS code with the code replacing DECA with the Kowalski simulator.


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 Post subject:
PostPosted: Sat Jan 20, 2007 2:07 pm 
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Joined: Wed Jan 17, 2007 1:04 pm
Posts: 2
Location: Rochester NY
hi GARTH
thanks , i see the newer processors have added features , but when i read kernal34's question it seemed like he might be asking about the syntax of the dec instruction , and why he was getting an error ( i can see i may have just misread what he was asking ) , i agree with using the newer chips

i am working on an SBC and just found this forum the other day , it has been an eyeopener for me as i wasen't aware of all the changes that have taken place , and i see i have been working with a ton of dated info :oops: , " too soon old , too late smart " :D , just trying to say this is a great forum and there is a ton of info here , i am really glad to see that WDC is producing chips , and that pulls are available at Jameco , thanks again , dana :)


Last edited by copperclad on Sat Jan 20, 2007 2:13 pm, edited 1 time in total.

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 Post subject:
PostPosted: Sat Jan 20, 2007 2:13 pm 
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Joined: Sun Aug 24, 2003 7:17 pm
Posts: 112
Actually the Kowalski assembler uses still another alias for DEC (without argument) and DECA, namely DEA!

The difference between

Code:
DEA


and

Code:
CLC
SBC #$00


is that DEA (according to the simulator) affects only the the N and Z flags while SBC affects also the V and the C flags. If your program does not care about the status of the V and the C flags (resulting from some previous operation) you can replace DEC (alias DEA) with

Code:
CLC
SBC #$00


or equivalent

Code:
SEC
SBC #$01



[/code]


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