Lots of interesting stuff here, y'all.
I would say that BDD and Chromatix's suggestion that the 6502 be used more as a source of control values for an independent IC or circuitry, not synthesis, seems simpler to implement for a beginner like myself. I think once I get the basics of digital electronics (hell, even just basic electronics…) down, all of the suggestions here will be quite instructive, and I'll be able to tackle more CPU-intensive solutions. I’ve always had the unhelpful urge to jump into the deep end before I'm ready, which I'm trying to control at the moment.
That being said, I do have a quick question or two about Chromatix’s proposed sample-oscillator design.
Chromatix wrote:
The next option is to do DDS using a largish RAM chip and a free-running counter, in which you can adjust the value added per cycle, the wrap address and the wrap decrement under CPU control. The counter should have more bits than the RAM chip has address lines, and you just use the high-order ones (for better frequency precision).
1. Do I have it right that because you’re only using the, say, the higher 8 bits of a 16 bit counter, increasing the value by which the counter increments is more precise/granular because the upper bits will be flipped slower than if it were an 8 bit counter?
2. Is there a way to ensure that wrapping over the sample table will happen at zero-crossings in hardware? Obviously if you did this you wouldn’t be able to represent completely arbitrary waveforms, but it might be nice to have at least some kind of mode that does this so that modifying the sample memory during playback won’t risk gnarly clicking.