BigEd wrote:
If the machine's crash rate is unchanged at slightly high and slightly low VDD, it's more likely to be a digital problem, otherwise more likely to be a timing problem.
Both POC V2.0 and V2.1 behave in a similar fashion, although V2.1 seems to be a little more prone to having its apple cart upset. I have both of them powered off the same power supply, which also has POC V1.1 connected. V1.1 is rock solid.
Ergo the power supply is not a likely culprit, which conclusion is bolstered by the five volt output being 5.02 volts.
Although V2.0 and V2.1 are somewhat different designs they share a lot of common elements. Both are equipped with the same amount of RAM, same amount of ROM, both have four serial I/O channels and both use a Microchip (Atmel) ATF1504AS CPLD for glue logic. The RAM and ROM is wired into the system in the same way with both units, and many other design elements are adaptations of what has already been proven in V1.1.
The principle differences between V2.0 and V2.1 are:
- V2.0 uses a quadruple UART (QUART) for serial I/O. V2.1 uses two dual UARTs (DUART). The pair of DUARTs theoretically contributes slightly more to bus loading.
- V2.0 uses a basic wired-OR IRQ circuit that is identical to that used in V1.1. V2.1 uses a triple input AND gate to drive the MPU's IRQB input high or low, with each gate input wired to a separate interrupt source.
Attachment:
File comment: POC V2.1 Enhanced IRQ Circuit
poc_v2.1_irq_ckt.gif [ 13.9 KiB | Viewed 1415 times ]
Not shown in the above are the pullup resistors attached to each of U5's inputs.
- V2.0's glue logic has five total I/O chip select outputs, one of which is wired to the QUART. V2.1's glue logic has six I/O chip selects outputs, two of which are wired to the two DUARTs.
Comments about timing have caused me to revisit the CPLD code to see if I may have inadvertently set up a race condition that is causing instability. I did see some aspects to the way in which chip selects are determined that could be improved, and ended up doing a significant amount of editing to the logic for V2.0. V2.0 is a better guinea pig for testing at this point because the I/O chip selects are simpler than those of V2.1.
Anyhow, after a number of studying, editing, studying, editing... cycles, I ran simulations on all important logic features, the graphs of which will follow.
By way of explanation, POC V2 has the following architecture:
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File comment: POC V2 Memory Map
memory_map.gif [ 8.49 KiB | Viewed 1415 times ]
At power-on or reset, the memory map exposes ROM at $00E000-$00FFFF—referred to as HIROM, and I/O at $00D000-$00D7FF—this is the default memory map. The "hardware management unit" (HMU), which is a virtual device inside the CPLD that is addressable at $00DFxx (the lower eight bits of the address aren't decoded), can modify the memory map as follows:
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File comment: Hardware Management Unit
hmu_map.gif [ 16.48 KiB | Viewed 1415 times ]
In the above, HIRAM ("high RAM") refers to RAM at $00E000-$00FFFF.
At power-on or reset, all bits in the HMU are cleared, which causes the default memory map to be selected and write-protection of HIRAM to be turned off. Another feature is a write to ROM will "bleed through" to RAM at the same address. This feature makes it possible to shadow the relatively slow (55ns) ROM into much faster SRAM (10ns).
Next, I will present images of the simulations I did on the logic. These will run to several posts, due to the limit on the number of images that can be attached to one post.
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File comment: Read from "base RAM" at $000000
basram_000000_read.gif [ 159.26 KiB | Viewed 1415 times ]
In the above, a read operation has been performed from "base RAM," which is RAM from $000000-$00BFFF. The read operation starts at vector 19 on the fall of Ø2 (second from the topmost row). At vector 20, the MPU places an address on the bus, VDA goes high and the CPLD reads D0-D3 for the bank bits, which are %0000. So the decoded address is $000000. RAM0, which is the SRAM mapped in from $000000-$07FFFF (512KB), is selected. All of this happens while Ø2 is still low, as the CPLD has a 10ns rating.
At vector 22, Ø2 goes high and the CPLD asserts the /RD (read data) line. RAM0 responds by driving the data bus, which can't be illustrated in this simulation, since it only represents what the CPLD is doing. At vector 24, Ø2 goes low once more and the read operation ends.
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File comment: Read from "extended RAM" at $010000
extram_010000_read.gif [ 155.94 KiB | Viewed 1415 times ]
In the above, a read operation has been performed from "extended RAM" at $010000. The sequence is identical to the previous, except the bank bits at vector 20 are %0001, which the CPLD decodes as $010000. RAM0 is selected, since the decoded address is in the range $000000-$07FFFF.
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