One of the things which isn't really obvious to me is what happens in the hardware when a page boundary is crossed in the 6502 processor for the INC instruction. I get that we do an initial fetch on the address bus as if the page boundary hadn't been crossed, but I don't get what exactly the hardware does to inform itself that the page boundary has been crossed, and thus, needs to correct the high-byte on the address bus.
I began looking at this with the absolute indexed INC instruction (7 cycles). From what I can tell from the visual6502 simulation, starting from when we get the low-byte in DL (2nd cycle of executing INC), we:
1. Put DL -> BI (low byte), put IX/IY -> AI, increment PC and update AB to read next byte; Add the two together (1 cycle; Carry output (I'm assuming) is signal for future cycle to need to correct the high byte).
2. Put DL -> ABH (high byte), ADD -> ABL (low byte), DL -> BI, 0 -> AI, Add w/ carry (increment) AI/BI -> ADD; Basically this is acting as-if we didn't cross the page boundary, but preparing for if we did.
3. Here is where I get confused. Looking at the data, we shove ADD (which is our incremented high byte) into AI, and then add by BI which we set to FF probably using the inverter (-1). Within the first half-cycle, it appears that if ABH needs updated because of the low-byte carry, it is then updated. (Makes sense when this is happening, because the busses are busy on the second phase of the clock cycle because of precharge MOSFETs.)
My question is this:I don't see any timing control change between an absolute indexed INC either crossing or not crossing the page boundary (DPControl doesn't differ, plaOutputs doesn't differ, the only thing that differs is the values in the adder [obviously], the output of the carry [obviously], and the high byte is corrected [obviously]). I don't understand how this is implemented in the hardware. Is this basically a special case, and somewhere in Random Logic Control there is a flip-flop that stores whether or not we want to take the high byte?
Furthermore, why can't INC be optimized for not crossing a page boundary if some of other instructions are? Is it simply to reduce complexity?
Provided, you can find a spreadsheet of the visual6502 simulation output for both crossing and not crossing a page boundary with INC, with the cycle that is confusing me highlighted in yellow.
https://docs.google.com/spreadsheets/d/ ... sp=sharingAny help understanding this would be much appreciated.