One little fun fact about the SNES CPU, the speed is often quoted as 3.58Mhz, however that is the maximum speed. It also can run at 2.68Mhz, and most SNES games were released on cartridges where the cheaper ROMs only supported 2.68Mhz. Like BDD mentioned, it slows down to 1.79Mhz during port access, and also there are DRAM refresh cycles that periodically halt the CPU. Years ago before I knew all that, I tried writing some timed code to make a bit-banged UART over the controller port. You can imagine how well that worked out..



It's an obscure system, but you might like the VTech CreatiVision. It has a 2Mhz 6502, with those TI video/audio chips.

I've been a programmer since I was 9 (~36 years). Over 20 of those have been professional (paid). So it's a good thing I have a thick skin or I could have been offended by that.





Yep, I'm familiar with that system. It's on my radar to collect when I can find one. Too bad there weren't many games made for it because those are some good specs for the day.

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Cat; the other white meat.

That was not directed at you --- that was not directed at any particular person.

I meant that, nowadays, most programmers are script-kiddies --- this is well-known --- this is why Python is the most popular language on desktop computers.

I'm pretty sure a script kiddie is someone who doesn't write their own scripts, and just uses ones someone else has written.
If you consider Wikipedia any kind of help, that seems to be their definition.

If this is correct, calling someone who writes their own code a script kiddie is both incorrect and a nasty insult.

Wikipedia's definition is the likely correct one, as it's the one I've known ever since I started with UNIX in the early 1980s.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

It seems clear to me - but evidently not clear to you, Hugh - that throwing in controversial statements is not a way to encourage thoughtful discussions and mutual enlightenment, or a way to keep a discussion on track. It is a way to get some response, yes, but not the kind of response which ultimately results in cooperative and supportive exploration of a 6502 interest. There are places you can go where the idea is to have an argument, and the more heated the better, but this isn't the idea here.

I have a Digilent Nexsys 2 board https://reference.digilentinc.com/reference/programmable-logic/nexys-2/reference-manual, which has a 100-pin Hirose FX2 expansion connector. It occurs to me that I could get a pretty cheap daughtcard PCB made with little more than a mating connector, 65C02 and power decoupling cap.

The 65C02 can run at 3.3V, and the Xilinx Spartan 3E can drive 3.3V I/O. Are there any landmines I'm not seeing?

Might wanna doublecheck what voltage the Spartan 3E attains for a logic high. In this regard 65C02's made by WDC are fussier than others. On most inputs the w65c02s wants at least 70% of Vdd, and inputs PHI2, IRQB, NMIB and RESB ostensibly require Vdd - 0.4V (although I'll bet there's wiggle room on this).

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks for the tip.
I'm admittedly unfamiliar with reading DC Characteristics... but it looks like, from the Spartan 3E datasheet https://www.xilinx.com/support/documentation/data_sheets/ds312.pdf page 121, that for LVCMOS33:


So the way I'm reading this is that the min Voh from the FPGA is >= the min required by the 65C02, and the max Vol from the FPGA is <= the max required by the 65C02.

Does this look ok to you, too, or is there more to investigate?

Uh... both!

Seriously, I agree the issue of voltage levels will be OK. But I ended up browsing through that Xilinx document you linked, and there's a LOT of detail (partly because the 3E has so many options regarding I/O characteristics). It seems certain the 3E can provide appropriate I/O for your project -- which sounds pretty cool, btw -- but you'll need to know what you want and how to ask for it.
(LVCMOS33 is not the default)

(Current required to drive an input on a 65C02 is practically nil -- basically just enough to charge & discharge the input capacitance. Minimum slew rate is probably also OK, except perhaps on the pin that drives PHI2.)

ETA: 5 ns is what WDC lists as the slowest permissible Tr and Tf (rise time & fall time) for the w65c02s PHI2 input. AFAICT the other inputs have no maximum Tr / Tf spec.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks! I've noodled around with FPGAs for a while - this is my 3rd board from Digilent, and I've had it a few years but haven't done anything beyond generating a video signal and lighting the 7-segment displays. I know how the IOSTANDARD is configured, so no problem there. I'm pretty confident when it comes to the digital side of things, but I've never developed competency on the analog side beyond what was required to get me through transistor electronics at university.

I'll be sure to select the slow slew rate.

One other question: Would you think any of these signals will require terminating resistors (assuming 2MHz 6502 clock)? I was thinking these would be point-to-point links, and so would not require termination, but the total traces length from the FPGA to the 6502 will, I imagine, be in the order of 50-75mm.

Of all the 65C02 pins, PHI2 will be the fussiest about signal integrity. I suspect that's the only one you might need to worry about -- and even that concern is probably unwarranted if you're using the slowest slew rate. But I admit I'm guessing. I didn't check what the FPGA's slowest slew rate is. (Of course if the slowest rate means Tr & Tf > 5ns then you'll have to select a rate that's faster.)

If I were in your shoes I'd simply ensure the PHI2 trace is as short as possible. Orient the 65C02 in a way that places its PHI2 pin closest to the connector from the Diligent board. And I'd recommend a PLCC package, not DIP. You might also allow some room for a terminating network (on the opposite side of the board, perhaps) but I have a hunch it'll be unnecessary.

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

If I recall correctly, and all the various data sheets have a tendency to run together, the lowest current setting per output is 2mA. With a suitably configured CMOS-based system, this value may still provide a respectable slew rate.

(The FPGA IOBs control voltage and current, which relates to the slew rate by virtue of the capacitance attached to the pin. I suspect that, in most situations, the capacitance an output pin sees is predominated by the sum of the capacitance of inputs it is driving.)

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Michael A.

From the Nexsys 2 user manual:
Any red flags here?

Because the series resistors are a form of termination I'm even more inclined to suppose you'll need to add no termination of your own.

2 mA is indeed the minimum, Michael. And it seems sensible that current would relate to slew rate according to attached capacitance (if I'm reading you properly), but apparently with this chip you get to make a choice of slew rate that's independent of your choice for current setting. (But excessive capacitance could override the Fast setting, I suppose.)

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html