GARTHWILSON wrote:
Actually that does sound pretty simple. If I understand you right: At the simplest level, the µC may not even need an MISO connection, since all it has to do is watch for when its SPI slave port is selected, then take the first byte and then select the right subaddress accordingly.
Sorry -- I haven't had time to draw up my idea in schematic form since today was my last day working for my (now former) employer. I should have more time to draw up some schematics to make things a tad bit clearer.
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The data to and from the sub-bus do not go through the µC, but rather through the buffers, which are also disabled by the same line that selects the µC's SPI slave port. Further steps would require the MISO line on the µC so it can, as you suggest, answer the SBC's identify or interrupt-status queries.
This sounds reasonable. I never thought of using the switch idea to replace the ADMIN line. The overhead is that now EVERY packet has to have that prefix command/address byte, but that would have happened anyway at some level. And, it's a lot faster than having to command the admin phase to change sub-addresses, then switch over to the normal device (1 byte overhead replaces, minimum, 2 or 3, plus the time taken to assert and negate the ADMIN line).
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I don't see this as needing an ADMIN line. The first byte sent to the switch tells it what to do, whether to just enable a device on the sub-bus, send ID, tell of interrupt status of devices on the sub-bus, disable sub-bus interrupts, or whatever. The controller can talk with the switch µC until a sub-bus device is enabled. After that, the switch takes no more instructions until its select line goes false and back true again.
I LIKE this. Again, I never thought of this, but it makes perfect sense. This isn't too far from GPIB's overheads either, where every transaction on the bus was prefaced with ATN asserted and the appropriate TALK/LISTEN commands. In some senses, it's actually
faster than GPIB.
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I'm assuming pin 1 is at the top of the list (e.g., pin 2 is CS1\)? Also, I'm assuming CS1 is the actual device select line?
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The next standard size of IDC up from 20 is 26. Here I'm abandoning the twisted-pair ribbon cable and baluns since you say the IDE cables can go well over 100MB/s without them.
Yeah, well, I'm also talking about the 80-pin IDE cables, not the 40-pins.
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I haven't pulled any 80-pin IDE IDCs apart to see how the interleaved grounds work. I think it might be necessary to do this before making this decision, to see how it'll all piece together.
Also, it looks like the characteristic impedance for such a cable is close to 260 ohms (if used balanced) or 130 ohms unbalanced.
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The exact software protocol for the switch can be determined later, and won't hold up my construction of the serial bus for my workbench computer mezzanine board.
Yeah, this seems reasonable. If changes need to be made, though, it's probably better to use a different connector or bus protocol completely anyway. I mean, 20 pins is already an awful lot!
![Smile :)](./images/smilies/icon_smile.gif)