Hey All!

Which logic family out of AC or ACT would be best in mixed environments that could have TTL, CMOS, NMOS or whatever else might commonly crop up?

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Bill

In a mixed environment you'd want ACT. Its intended purpose is to accept TTL levels, but it'll accept CMOS levels as well.

Be aware that AC and ACT families have very fast rise and fall times on the outputs. This makes them less forgiving in regard to your supply bypassing and the wiring techniques you're using. See the thread Techniques for reliable high-speed digital circuits

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Thanks Jeff.

I'm am aware of that, but they also have two qualities I need. Speed and drive capability. I'm trying to keep the total propagation delay in the chip select logic down under 20ns.

In the final version of this project the PCB will be a 4 layer with ground and Vcc planes and compact layout. As well, there will be 0.1 uF and 0.01 uF bypassing for each chip. The bus will also incorporate parallel ac termination. I'm hoping to be able to run this as close to he 14mHz limit as possible.

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Bill

Ah -- sounds like a new 'C02 or '816 project, then. Sweet! And I guess you know that, in practice, the 14 MHz "limit" can be exceeded by a wide margin (albeit in violation of published specs).

Done right, a four-layer board is wonderfully effective for dealing with fast edge rates. And two bypass caps per chip is overkill, I'd say (with 4-layer, at least).

Parallel ac termination is a workable solution but I hope you'll also consider alternatives.

• no termination. On a compact board this is satisfactory.
• no termination, and, where possible, replace 74AC/ACT logic with AHC/AHCT. These have speed similar to AC/ACT but with gentler edge rates (similar to HC/HCT).
• series termination (at the source) has lower parts count and power consumption than parallel ac termination (at the destination)

Re fast memory decoding, programmable logic is hard to beat -- but one thing comes close, and that's the tiny, superfast gates I posted about here.

Have fun, and keep us posted!

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

AC termination is probably best (and certainly easiest on the power consumption), if your lines are long enough to need terminations at all. But even with longer lines, terminations won't really do any good if they don't come anywhere near matching the Zo (characteristic impedance) of the transmission line. That means you have to control that too, with having the right thickness separating the signal line from the ground (or virtual ground) plane for the width of the line. To make the calculation easy, you can use online calculators like https://www.eeweb.com/tools/microstrip-impedance . When you get the board made, you have to specify that you have controlled impedances on it, and tell them what separation you want between layers so they don't just give you whatever laminates they have most of in stock. Further, if you get that impedance too low for the driver type to drive, that's a problem too. For example, if it's 100Ω, a 5V edge gives 50mA. Can your driver swing it? Diode termination works nicely, but I have not seen Schottky diodes that are fast enough for the job with 74AC.

It's much easier to just hold the size of the board down small enough that you don't need to worry about terminations at all. The post at viewtopic.php?p=33837#p33837 discusses how far you can go without terminations.

My page on avoiding AC performance problems, and the links inlined and at the bottom, should be helpful for these things too.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Great info, Garth! And I'll agree that, wrt power consumption, AC termination is far better than parallel or Thevenin -- which is maybe what you meant. Parallel and Thevenin are in a league of their own, power-wise -- very wasteful!

Thanks for the links; here's a clip from one of them.

Even though AC termination has minimal impact on power consumption, I believe the impact of series termination is even less. (Admittedly we're comparing numbers which are too small to matter except maybe in battery applications. Also, circumstances sometimes preclude the use of series termination.)

Care to comment? And, while we're exploring this, it occurs to me that series termination may actually result in a tiny power saving. Still mulling this over.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

It seems like series termination, if used on bi-directional lines, should be at both ends; but I don't have a clear-enough understanding to elaborate, and I have way too much work to do right now to take time to try to simulate it to come to a better understanding. (My regular job and a consulting job on the side both have rushes that coincided, although I think I'm about to dump the consulting job because of the extreme red tape involved in getting parts approved for satellites. Even at $100/hr, it's not worth my health.)

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Sorry to hear about the unfortunate coincidences in stress; hope things even out for you soon!

Agree again (although I don't think anyone mentioned bi-direction lines, so far). And it's a given that I, too, am working to improve my own understanding.

Regarding the power dissipation question it seems my intuition was correct. Delving into the document linked above I find, "While other termination circuits dissipate extra power, series termination reduces power consumption and dissipates less energy than no termination. This is a recommended termination scheme for the FACT family because of its low power dissipation."

There's a caveat, but it doesn't apply to simple point-A to point-B routing. Also, series termination assumes the transmission line's impedance is greater than that of the IC driving it. (The series resistor is made equal to the difference.) As Garth noted, "if you get that impedance too low for the driver type to drive, that's a problem."

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

Series termination does not have to be used at both ends. Well, it depends. Both series termination and AC termination need to be at both ends for bidirectional lines. Series termination needs to be at the transmission end for unidirectional lines, and parallel AC termination needs to be at the the receiving end. Series termination looks simpler but it uses power for the entire time the line is high. AC termination only uses power for the period of the RC time during transitions.

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Bill

Yup.

Referring to the image posted above, I wonder if you meant to say parallel termination.

Can you explain more about the buses on your project? Sorry, I guess I missed the implication of a terminated data bus (which of course would be bidirectional). Roughly how big, physically, would this bus be? And would it be all on one card, or using slots for plug-in daughter cards?

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html

I meant serial, but now that you mention it - both. Serial into what ever load is being driven , parallel into the load and ground. Parallel is certainly worse, but I was considering parallel ac termination.



Will do. Tomorrow. It's late...

_________________
Bill

So...

The idea is that there would be a 4 layer mother board. It would be divided up in to two sections. The main logic section and an I/O bus.

The main logic section would contain only the CPU, RAM, ROM and memory management logic and both I/O and memory select logic. The CPU will be a W65C02S, the RAM will be a 32KB .3" Winbond (or similar) SRAM, the ROM will be the fastest 128KB EPROM/EEPROM I can find. The memory management and some of the selecting will be handled by a 7.5nS GAL and a 74AC574. The I/O select logic will be handled by 2 74ACT138s or a 74ACT139 (depending on how ambitious I can get) that will be subordinate to the GAL, but not to each other. The aim is to have the delay in memory selects to be in sub 7.5nS range and the I/O selects in the sub 14nS range. I am currently measuring 13nS, so that goal has been reached.

The data buss in the main logic section will be laid out a short as physically possible and will have the CPU, RAM, ROM, the 74AC574 and a 74ACT245 on it. I figure I can make that 8cm or a bit shorter if I lay it out such the all the chips are side by side. I'm also considering a 'T' arrangement or a "+". Which do you guy's think would be best?

The I/O bus will be either 3 or 7 card slots with the data lines being driven by the afore mentioned 74ACT245. The slots will be 2cm apart. So if 3 slots, the bus will be about 5cm long, if 7 slots it will be about 13 cm long. The goal for propagation delay in putting data on the I/O bus is ~20nS and I have that working now. The other lines that will be outbound only on the I/O bus will be the I/O select lines and A0, A1, A2, Phi2, Reset and possibly others. Those not coming from the decoders will be put through another 74ACT245 with the same overall delay as the data bus. Incoming lines will include IRQ and NMI. These will be un-buffered.

Cards put on the buss will be buffered with select (for lowest PD) 74AC(T)245s so as not to extend the length of the bus into the I/O card too far.

Any help would be appreciated.

_________________
Bill

How 'bout parts on both sides? I have a project at work that I think will require putting parts on both sides, something I've been looking forward to for a long time, to increase my capabilities of achieving greater density. (My previous experience in putting parts on both sides has been very minor, with very few parts on the second side.)


One I had thought of doing was a backplane with connectors on both sides, like this

Code:

   ─┤
    ├─
   ─┤
    ├─
   ─┤
    ├─

in order to keep it shorter while still giving enough room between cards. I don't know of any OTS card cages that are made that way though.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Given the rise time of 74AC outputs and properly tuned parallel ac termination, the actual current should not reach 50ma. Maybe half that. 74AC outputs should have no issue, so the I/O bus should be fine. The memory and CPU are another story. I'll have to try very hard to keep the lines short as I don't think much in terms of termination will be tolerated there. Components on both sides will be considered.

Anyway, I'll allow for the termination, but I'm going to make every effort to keep the buses, both sides of the buffers, as short as possible. Since each I/O board can have multiple devices on it, I'll be able to get away with only 3 connectors on the I/O bus.

Edit: I just noticed that the reverse recovery time for glass 1N60 diodes is just 1nS and they add only 2pF each. I must do some experiments.

_________________
Bill

Chips side by side sounds promising. And it might even be feasible to intersperse card-slot connectors among the side-by-side chips. Like: connector, chip, connector, chip, and so on. The advantage would be a shorter bus, overall. That's because the connectors need space between them anyway. Better to put that space to use rather than have it sitting there blank. But routing all the traces would be tricky, even with a 4-layer board.

It's not clear to me that termination will be necessary, but if you want to hone those skills maybe that's a good enough reason to do it. I also wonder about the necessity for a '245 on the data bus. I think it might be a good idea, but not to add extra drive for the I/O cards (that should be alright). Here's what does concern me. WDC CPU's are generally not specified as accepting TTL levels on their inputs; they supposedly need full, CMOS levels. That includes the CPU's data bus pins when it's doing a read. Unless all your memory and peripheral chips output CMOS levels (not merely TTL levels) then you might wanna consider placing an 'ACT245 between the CPU and the non-CMOS-level chips to act as a level-shifter. (Lots of people have ignored the WDC spec and gotten away with it, though. Also: if you don't wanna ignore the spec, another option is to place pullup resistors on the data bus.)

Can you share a sketch of that logic when you're ready, please? I think I might have a tweak that'll interest you.

-- Jeff

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html