Hello, all!

Sorry if this ground has been covered before, but I couldn't find anything quite like what I'm asking for so I thought I'd ask about it.

I'm in the early stages of planning a 6502 computer. I'm still pretty new to this sort of thing, so I'm not there just yet. The few requirements I have for the project are:

• Built from off-the-shelf, through-hole components that are still being manufactured.
• RS-232 serial as the only I/O (at least at first!).
• Runs enhanced BASIC.

Ideally, I'd end up with something a bit like http://searle.hostei.com/grant/6502/Simple6502.html, which looks capable of running EhBASIC, at least based on a first glance at that memory map.

I just wanted some pointers in the right direction, or words of advice.

Thanks!

Welcome! I think Grant's designs are an excellent starting point - you'll learn something by doing that, which you could apply to your own design if you go on to do that.

Have a good look also at Garth's site, he has lots of relevant notes for everything from soldering to coding.
http://wilsonminesco.com/6502primer/

I see Ed just posted, but I'll post anyway, since I already wrote it up:

See the 6502 Primer which is about building your own 6502 computer. It's in 22 logically organized chapters. The final one is a potpourri of related circuits, starting with a basic 6502 computer with a 65c22 VIA rather than a 6551 ACIA. Although lots more I/O can be added, it is simpler than Grant's, yet more expandable IIRC. There's nothing there that's specific to BASIC (the outstanding EhBASIC or any other), but I offer this since you're talking about building. There are several prominent members here who are quite familiar with EhBASIC, and are helpful. Unfortunately Lee died in 2013.

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http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

I have a design that uses only 4 chips + oscillator, and like Grant's uses a USB to TTL cable for terminal I/O and power. One unique thing about it is the use of a single NAND gate made with two 1N60 diodes and a 2N7000 mosfet. There are some things about it that "ain' too su-fis-ti-ca-tud", but what do you expect for 4 chips?

It has 32K RAM and 16K ROM. I believe all the parts can be found on eBay at any given time. The basic circuit could be modified down the road to include access to more I/O, but it might get your feet wet.

I even did a board layout of it that is only 86mm x 58.4mm - never built it past the breadboard stage though.

I have the firmware for it too(mini-monitor + EhBASIC), if your interested. Schematic is attached.

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Bill

The VCF 6502 badge had 2k of RAM, 16k of EPROM, and a bit banged serial port and it runs EhBASIC. EhBASIC will run on almost any 6502-based board as it uses minimal IO.

http://www.sunrise-ev.com/6502.htm

Daryl

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Please visit my website -> https://sbc.rictor.org/

Nifty design, Bill. Does it work well without a phase 2 qualified RAM '/CS' or '/WE' signal?

Indeed it does. I've used this scenario at other times for simple machines. It may be that the RAM specified has an access time of 20nS or better. I've never made 6502 machine that used slower than 120nS RAM and I have never had a problem with not using phi-2. That speed is maybe what mitigates the Phi-2 requirement. I'm guessing that the data hold time is plenty sufficient when using fast RAM. At least this has been my unbroken experience.

I could put a scope or a logic analyzer on it and see what the signals look like. I still have that circuit on an old Heathkit ET-3300 on one of my old project shelvs. Maybe I'll take it down and play with it a bit next week.

For anything serious though, with a busier bus (more I/O) and higher clock speeds, I do incorporate phi-2.

Edit: I just had a quick look the timing specs on the 6502. Another contributor is that in these simple designs I never have any added propagation delay (no gates) in the chip select so the fast RAM reacts to the address lines directly. This machine runs at 1.8mHz, so the typical data hold time is going to be around 33ns which is 3x more than enough time for 20ns RAM which has a chip deselect time of 10ns or less.

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Bill

I had pause to play around with this recently. The design I proposed is a race between the processor and RAM and does not work with all combinations of CPUs and memory I have on hand. It seems I have just being using the same processor and RAM chips that I keep at my bench for quickies.

So I ditched the oscillator can and replaced it with a 74LS00, two resistors and a crystal. The resulting circuit fully qualifies the RAM R/W with Phi-2 and is attached. I have tested it with RAM and ROM as slow as 200nS and as long as the 6502 you are using can keep up with a 1.8432mHz clock, runs like a charm. The BOM is still very light (5 ICs, 1 mosfet, 2 common Schottky diodes, 5 resistors, 1 monentary switch, 1 electrolytic cap (you might want to add a 100uF across the power rails) and 5 bypass caps. With that you get 32K RAM, 16K ROM and terminal I/O.

I also went a little further and came up with a very capable machine that fits in the palm of your hand by replacing the 74LS00 with a GAL22V10 .. but more on that in another post.

Improved minimal EhBASIC machine:

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Bill