banedon wrote:
I've been thinking of ways to implement a way of attaching a module to a 65C02 PCB and have the attached Microprocessor on the module take over the system - including the ability to read/write RAM.
If you don't especially need lots of speed then you can save significantly on resources -- two octal tristate buffer IC's, perhaps, and certainly 16 pins on the attached device (eg: microcontroller) -- by NOT providing direct control of the 65xx address bus. The attached device would take over the 65xx
data bus, plus a few control signals, but not the address bus.
Six cycles are required for each byte written to the 65xx's RAM. The attached device places dummy instructions on the data bus, faking a LDA immediate and a STA absolute. For example, in order to write $12 to $3456 the bytes $A9, $12, $8D, $56, $34 are faked (placed on the data bus just as if they'd been read from RAM). The 6th cycle is a write cycle, and on this cycle the RAM
is allowed to participate, storing the byte we wanted stored.
Rinse and repeat!
Just be aware that, as you proceed, the 65xx Program Counter will be blindly counting through the entire 64K space. After the very last STA you'll probably want to restore PC to a meaningful value, either by faking a JMP or by applying a reset or interrupt.
Reading from the RAM can be done in a similar fashion, but each byte needs only four cycles (for a LDA absolute). The first three cycles are faked ($AD, $34, $12); then on the 4th cycle the attached device takes a peek to see what appears on the bus. On this cycle the RAM is temporarily allowed to participate -- ie, to read what's at $1234. [Enabling reads requires the nOE signal to be wiggled. Enabling writes is potentially simpler, as you may choose to let resistors be the default bus masters. During write cycles the CPU will override the resistors automatically. More on bus control in the posts below ].
You can also take control of the 65xx's I/O devices, since they read and write in the same way as RAM.
You could arrange to copy bytes from RAM to a UART, or vice versa -- IOW, a level-2 bootloader. Initializing the UART isn't a problem because that too can be faked with the cycle-by-cycle technique.
In fact, except for conditional branches the code-fake thing can do pretty well whatever you want!
Just remember when you're done to restore PC to a meaningful value.
-- Jeff
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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html