Some DMA questions for you all...

Does bringing the BE input low stop the internal clocking of the 65C02 & 65C816 or does the CPU attempt to continue running?

Specifically, if the CPU is running normal (fetching opcodes, and accessing memory in Read and write mode) and BE is brought low, will the system stop and wait for it to go high and continue on as normal, or will it continue on, seeing the value on the data bus as indeterminate/all 1's?

The technical documents say is that the "buffers are set to the high impedance state," implying that the CPU will not stop.

If the cpu continues to run, then the RDY line will have to be brought low also in order to preserve the CPU state.

Since the RDY line is bi-directional, what type of gate should be used to drive it low without affecting its output mode?

Does anyone have any practical circuit diagrams of this kind of DMA?

Thanks!

Daryl

I have no DMA experience, but I'll jump in since no one else has.

I don't see anything in the data sheet that even implies that the processor is stopped by the BE input going false. You could use RDY, or do what the Apple II did. The early 6502's didn't have a BE input. Pulling out an old Apple II book here, I see that in order to get the DMA function, they added buffer ICs on all the lines (bidirectional for data), and then the DMA line not only disabled the buffers but also stopped the clocking to the processor. Clearly you'd have to use appropriate logic to avoid having clock-high pulses that are way below the minimum time spec.. Also with the old NMOS 6502, the DMA couldn't steal more than a few cycles in a row or the microprocessor would start losing the contents of the internal registers. This is not a problem with WDC's processors, which allow stopping the clock as long as you want in either phase without losing data.

> Since the RDY line is bi-directional, what type of gate should be used to
> drive it low without affecting its output mode?

The data sheet says it has an active weak pull up, that it is only pulled low internally by the WAIt instruction, and that otherwise is an input. I take it to mean that as long as your circuit doesn't pull it up hard, you're ok. For example, LSTTL can't pull up very hard. Since the internal pull-up is a weak one, you can pull down as hard as you want, like with some logic ICs that can pull down 25mA or more.

If you use cycle-stealing though, remember it will fowl up timing on 65c22 timers if their reference is phase 2. If you use the 65c22 timers to get accurate timing, you may have to work it to count pulses on PB6 from an external source instead of using phase 2. Further, this external input will have to be slower so pulses are not missed while phase 2 is not toggling. There will be other effects too, like shift rate jitter on the 65c22's serial port in modes where the shift clock is controlled by phase 2, and probably a lot more I'll think of after I post this. DMA has its place, but make sure you take everything into account. I suppose it's used most for disc drives, but I've never worked with them. The 6502 has outstanding interrupt performance, which may often make DMA unnecessary. Wait states is another area I have avoided for similar reasons. My next workbench computer will have no ROM directly on the processor's bus, since maximum ROM speeds are not very fast.

Garth

Garth,

I'm confused; are you saying that RDY should not be tied to +5V? I did that on my hobby SBC because I didn't realize the RDY had an internal pullup. I'd think that tying RDY to the +5V would simply make any pullup resistor on the same line moot.

Scott

> are you saying that RDY should not be tied to +5V?

According to the book, any output is only guaranteed to sink 1.6mA at .4V when pulling down; but my Rockwell VIAs, although their spec says the same thing, will actually sink about 110mA when shorted to +5V. Assuming that's the case here also, if you execute the WAIt instruction and leave the processor in that state for long, the internal heating will probably destroy it. But how many of us use the WAI? One use is to save power when not busy; but your entire board normally only takes a few mA. Unless someone's trying to get several weeks of continuous operation from a 9V battery, it's probably not an issue. The other use of WAI is to get the fastest possible interrupt response when the processor is not busy. The 6502's interrupt response is already excellent compared to other processors, and so far I have not had such a great need to improve it so as to justify stopping everything else for it. Please take these comments as only observations from the data sheet and as brainstorming. I can't claim much authority from experience on this one and I don't think I'll be doing destructive testing anytime soon to check the vulnerability of the RDY line when it's an output.

Garth

So it sounds like single-65C02 systems should let RDY float or pull it up through 2.2K ohms.

Sure is a lot of chaos here. 6502 handled RDY one way, R65C02 didn't even have a BE input (though R65C102 did?), neither Rockwell processor had the WAI instruction, and while the W65C02S has WAI, RDY, and BE the W65C02C splits RDY's functionality into two pins???

This all sounds very ad hoc, probably for specifically targeted consumer products along the way. No wonder most designers would shun DMA designs and just rely on interrupt-driven block I/O when they want more performance than polling approaches afford.

Didn't some designs simply use fast RAM and do DMA on the opposite phase of the system clock, getting a single "free" DMA channel that way?

It looks like WAI was meant as a "service request" instruction. Say a 2 CPU system where the "slave" ran user programs. When a slave program did a WAI the master would be interrupted and could suspend the slave and float it, then by checking a "mailbox" in the slave's address space determine what was being requested and perform or initiate the service (I/O request, etc.). This way the slave has no direct I/O access and needs only minimal reset logic and a null (or no) interrupt handler. The "operating system" would live over in the master CPU's address space and run there exclusively.

Sounds like a pretty vanilla multiprocessor design, and a 65C816 would make a nice master supporting many 65C02 slaves all located within its extended address space. Of course I haven't a clue what you'd use it for.

> Sure is a lot of chaos here. 6502 handled ...

There are plenty more, like that WDC's has a VP (vector pull) output (on pin 1 of the DIP, which used to be a ground, of all things!), a ML (memory lock) output pin for multi-processor designs, and various levels of instruction set enhancement over the years. Pin 35 of the DIP is still NC; and as speeds rise, it will almost have to be turned into an extra ground pin. Then there's still the SO input, whose obscurity everyone apparently respects by not using the pin. It wouldn't bother me a bit if they'd do something more useful with that one. How about an output that would tell when it was beginning a dead bus cycle; ie, when the only operations taking place are internal to the processor. Then you could have (limited) cycle-stealing for the DMA without stopping the processor or the phase 2 at all. Better yet, how 'bout if they eliminate all the dead bus cycles and... uh-oh, now I'm getting carried away again.

Garth