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PostPosted: Tue Nov 14, 2017 7:11 pm 
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WDC just posted this on facebook:
https://www.embeddedadvisor.com/magazin ... IP_Design/
(The magazine's website is https://www.embeddedadvisor.com/ )

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There's an article about WDC starting on page 10. The subsequent article starting on page 14 ranks WDC in the top 20 IP and design solution providers.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?


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PostPosted: Tue Nov 14, 2017 8:57 pm 
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Thanks for sharing. A quote:
Quote:
[The CMOS 65xx series] Continuing to be a popular CPU in embedded sytems, including for example low cost games, medical equipment and car dashboard controllers.


I see a rather amusing alternate take on the Furber/Wilson visit which resulted in the ARM architecture and implementation at Acorn.

I notice from another thread that WDC have licensed a 6502 core for Lattice FPGAs running at a respectable 75MHz.

Also perhaps of some interest, a mention of the Mostek 5065 microprocessor, from the 6800 team in Motorola before they designed the 6800, originally a custom micro for Olivetti.

Quote:
MOSTEK 5065's By THE 1000's

The Mostek 5065 microprocessor, designed specifically for a realtime, interrupt response environment, such as telecommunications, is currently being shipped in "thousands per month" quantities according to Ken Davis, spokesman for the Carrollton, TX based microprocessor manufacturer. Quantity shipments actually began back in February of 1974.

Briefly, the 5065 is a single chip, 40-pin, 8-bit parallel PMOS microprocessor, equipped with 51 instructions. Execution time ranges from 3 to 16 Us. Several unique architectural features have been incorporated' into the 5065 design. Foremost is the triple level architecture, so called because the processor chip triplicates the program counter, accumulator and the carry/link bit. This permits program level switching to occur immediately without the usual machine status saving overhead. Another design feature of the 5065 is its multiple indirect addressing capability.

The basic instruction format supports several addressing modes, including direct (to page 0), page relative and indirect addressing. Furthermore, the left-most bit of an indirect. address is used to indicate further indirect references, such that a chain of indirect addresses can be implemented. This feature has the effect of limiting the memory addressing range of the 5065 to 32K bytes.

Other features include a 256 byte RAM stack (page 1) which permits 128 levels of subroutine nesting, DMA capability via a WAIT signal input, and on-chip decoding of control signals to facilitate I/O interfacing. Supply voltages are +5, -5 and -12 V.
Supporting development tools include a cross assembler, installable on a l6-bit minicomputer (available for $100) and an evaluation board (2Q75) complete with clock, 512 ROM, lK RAM bytes, UART for TTY and a very usable systems development aid called PAR (Program Aid Routine). PAR provides a console debugging facility through the TTY, complete with loader, single step, display, alter, breakpoint, etc., features of a debugger program. Mostek supplies their customers with complete documentation for a build-it-yourself hardware development system.

The 5065 is immediately available in production quantities. CPU chip prices are $58 in quantities of 100 to 499 pieces. The evaluation board will be priced in the $800 range.

(Microprocessor Digest Feb 1975)


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PostPosted: Wed Nov 15, 2017 7:27 am 
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Quote:
Furthermore, the left-most bit of an indirect. address is used to indicate further indirect references, such that a chain of indirect addresses can be implemented.
That's an interesting approach. A single opcode can then be used for any level of indirection.. very flexible.

(Can't read the OP article yet - Fortinet blocks it because it's a 'new' domain. Trying to get it re-evaluated now. [Update: At least Fortinet was quick about it - I can read it now])


Last edited by Tor on Wed Nov 15, 2017 8:37 am, edited 1 time in total.

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PostPosted: Wed Nov 15, 2017 7:42 am 
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It turns out - I very vaguely remembered this - that other machines have used the idea of iterative indirection. From Wikipedia:
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The IBM 1620, the Data General Nova, the HP 2100 series, and the NAR 2 each have such a multi-level memory indirect, and could enter such an infinite address calculation loop. The memory indirect addressing mode on the Nova influenced the invention of indirect threaded code.
The DEC PDP-10 computer with 18-bit addresses and 36-bit words allowed multi-level indirect addressing with the possibility of using an index register at each stage as well.


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PostPosted: Wed Nov 15, 2017 8:10 am 
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Most ideas in microprocessors have indeed been tried out already on minis and mainframes in the past.


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PostPosted: Wed Nov 15, 2017 8:43 am 
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Quote:
Mensch calls the life support devices "very personal computers"
Can't argue against that! VPC it is.


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