Apple II and 6522
Re: Apple II and 6522
I wonder if it's worth checking the reset input of the VIA - or even tying it off inactive. A glitch on reset could cause your symptoms, I think.
Re: Apple II and 6522
You're not accessing the 65C22 registers via the 16 "device select" addresses associated with the "slot" you're using?
Re: Apple II and 6522
I'm not familiar with the Apple II, that's why I hesitated to post in this thread.
The interesting question is, if DDRA is set to $00, or if it contains a "random value" when getting corrupted.
If DDRA is set to 0 (all PA Bits are inputs), then BigEd is right about checking the /RESET signal.
If DDRA is set to something different from $00, then to me it looks like a timing problem, which happens during write cycles.
The WDC W65C22N datasheet says: address, /CS and R/W have to be stable >10ns before the rising edge of PHI2,
and they have to stay stable for >10ns after the falling edge of PHI2.
The old Rockwell R6522 datasheet says: for the R6522(1MHz) address, /CS and R/W have to be stable > 180ns
before the rising edge of PHI2, and they don't have to be stable after the falling edge of PHI2.
So if something goes wrong during a write cycle, it could happen at the rising edge or at the falling edge of PHI2.
;---
My suggestion would be to try an old 6522 chip like the R6522, and to see if DDRA is getting corrupted, too.
If yes, would it be possible to solder a wire to the PHI2 output of the 6502 for feeding the PHI2 input of the 6522 directly ?
The pinout of the 6526 isn't too different from the pinout of the 6522.
But for the 6526, the write timing is supposed to be more simple because it's only related to the falling edge of PHI2.
Maybe trying if the data direction register of a 6526 is getting corrupted too might be helpful...
The interesting question is, if DDRA is set to $00, or if it contains a "random value" when getting corrupted.
If DDRA is set to 0 (all PA Bits are inputs), then BigEd is right about checking the /RESET signal.
If DDRA is set to something different from $00, then to me it looks like a timing problem, which happens during write cycles.
The WDC W65C22N datasheet says: address, /CS and R/W have to be stable >10ns before the rising edge of PHI2,
and they have to stay stable for >10ns after the falling edge of PHI2.
The old Rockwell R6522 datasheet says: for the R6522(1MHz) address, /CS and R/W have to be stable > 180ns
before the rising edge of PHI2, and they don't have to be stable after the falling edge of PHI2.
So if something goes wrong during a write cycle, it could happen at the rising edge or at the falling edge of PHI2.
;---
My suggestion would be to try an old 6522 chip like the R6522, and to see if DDRA is getting corrupted, too.
If yes, would it be possible to solder a wire to the PHI2 output of the 6502 for feeding the PHI2 input of the 6522 directly ?
The pinout of the 6526 isn't too different from the pinout of the 6522.
But for the 6526, the write timing is supposed to be more simple because it's only related to the falling edge of PHI2.
Maybe trying if the data direction register of a 6526 is getting corrupted too might be helpful...