BigEd wrote:
Very interesting! (32-bit microsequenced engine uses 2 block RAMs presumably for microcode.) Looks like the idea is to keep the code proprietary and license it commercially?
Quote:
The next project will probably be to see how many MCL65 cores I can stuff inside of a Spartan-7 FPGA. If I can time-share sixteen cores inside of one physical core, have two cores share microcode and program RAMS, and instantiate 32 of these blocks, then I could potentially reach 1024 cores in this modest FPGA. Stay tuned!
After that I may investigate implementing a super-scalar microsequencer which can issue more than two instructions per clock cycle.
Yes, it appears to be a proprietary/commercial core, the same was true for the MCL86 8088 core. It provides an interesting optimization goal for anyone developing a new core though.
The time-share idea sounds interesting, though he'll have to do something with the stack page, 32 time-shared cores all trying to manipulate the stack, hmmm.
The super-scalar microsequencer sounds interesting, and is something I've put some though into in the past. The tricky bits will be separating the opcodes from the instruction queue (made tricky by the 6502's multi-byte instructions), and the handling of self modifying code.
Quote:
As a size reference, this was the result of
Electric Eye's fitting adventures on a spartan 2:
Code:
flops slices LUTs RAM16 HDL Notes
cpu.v 155 276 474 8 verilog by Arlet Ottens
Arlet's core may be smaller,̶ ̶a̶t̶ ̶l̶e̶a̶s̶t̶ ̶i̶n̶ ̶L̶U̶T̶S̶,̶ ̶t̶h̶o̶u̶g̶h̶ ̶e̶v̶e̶n̶ ̶t̶a̶k̶i̶n̶g̶ ̶t̶h̶e̶ ̶S̶p̶a̶r̶t̶a̶n̶-̶7̶'̶s̶ ̶l̶a̶r̶g̶e̶r̶ ̶b̶l̶o̶c̶k̶r̶a̶m̶s̶ ̶i̶n̶t̶o̶ ̶a̶c̶c̶o̶u̶n̶t̶,̶ ̶t̶h̶e̶ ̶M̶C̶L̶6̶5̶ ̶h̶a̶s̶ ̶a̶ ̶5̶0̶%̶ ̶a̶d̶v̶a̶n̶t̶a̶g̶e̶ ̶i̶f̶ ̶I̶'̶m̶ ̶d̶o̶i̶n̶g̶ ̶t̶h̶e̶ ̶n̶u̶m̶b̶e̶r̶s̶ ̶r̶i̶g̶h̶t̶.
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