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PostPosted: Sun Sep 24, 2017 8:30 pm 
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I want schematics of the original MOS 6502, but gate level. I don't know how to read silicon and understanding transistor schematics is so hard for me. Where can I find these?


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PostPosted: Sun Sep 24, 2017 8:39 pm 
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to be honest, I don't think such a thing exists. If nothing else, the original NMOS 6502 relies on transistor functionality that cannot be represented in terms of pure logic gates.

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PostPosted: Sun Sep 24, 2017 8:47 pm 
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Yes, AFAICT much of it was designed at transistor level - and all of it was implemented at transistor level. No cell libraries, no ready-made NOR gates. Every transistor size considered. And indeed, some transistor-level circuits which don't readily admit a logical equivalent.


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PostPosted: Sun Sep 24, 2017 11:02 pm 
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A major portion (or maybe all) of what they mean by "transistor functionality that cannot be represented in terms of pure logic gates" is that there are a lot of transistors used as bidirectional signal switches, through which signals can pass either direction, acting much like a 4066 analog switch IC.

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PostPosted: Mon Sep 25, 2017 5:13 am 
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Forum member 'org' did a lot of work aiming to create a logic level description of 6502:
viewtopic.php?f=8&t=2208

I don't know if it was completed, or if it was then well-tested. At least, it gives an idea of how much work it is to do this.

Another approach would be to take a well-regarded HDL model, such as Arlet's, and extract a logic-level description from the FPGA tools. It will not be pretty, and will not be a recreation of the original 6502 design, but it will be just as accurate in its behaviour as the HDL model.


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PostPosted: Mon Sep 25, 2017 5:44 am 
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BigEd wrote:
will not be a recreation of the original 6502 design

Which raises an important question. LBSC, do you consider it necessary to reproduce the behavior of some or all of the NMOS undefined opcodes?

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PostPosted: Mon Sep 25, 2017 5:45 am 
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There's also Andrew Holme's FPGA implementation, built from netlists extracted from Visual6502: http://www.aholme.co.uk/6502/Main.htm (announced on 6502.org here: http://forum.6502.org/viewtopic.php?f=10&t=4295).


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PostPosted: Mon Sep 25, 2017 6:03 am 
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Oh, well remembered! I'd forgotten that effort. The end result is logic, in verilog form, very closely matching the 6502 implementation, looking like this:
Code:
assign o[1586] = i[1620]|i[1609]|~i[1675]|i[1536]|~i[1300]|i[541]|i[119]|i[927];
assign o[1219] = ~i[1620]|i[1609]|~i[378]|~i[1675]|~i[927]|~i[1300]|~i[541]|i[996];
assign o[979] = ~i[24]&i[546];
assign o[19] = ~(~i[660]|~i[559]);


Which probably underscores the point that what a minecraft re-implementer probably really wants is something nicely laid out in two dimensions. I think that work is work which is yet to be done. Designing and laying out a 6502 in minecraft might be about as much work as originally laying it out in ruby lith - which is not to say it can't be done, just that it is a big project. But I don't know, perhaps there are tools to help.


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