Yes, but how does the CU steer the incoming bytes into the corresponding places?

There's more than one way to arrange things...

In a mux-based system, a register which might read from two sources would have a mux on the input, with a control line. Raise it, and the register reads from one source, lower it and it reads from the other source.

In a shared-bus system, the register would read from the bus, and one or other of the sources would be selected to drive the bus. The source which doesn't drive the bus has its outputs tristated. In this case, there are two control lines, which enable (or disable) the drivers on the two sources.

In an OR-based system, the two sources would feed their outputs to a bank of OR gates. The selected source drives its value, the other source drives a zero. The output of the OR gates is the desired value and is driven to the receiving register.

In most cases, the register also needs a control signal to say whether it should load a new value or should retain the old one.

It's possible to combine these ideas, such that
- if source A is selected, then its value goes to the register
- similarly for source B
- if neither source is selected, the register retains its present value.

BigEd
Ooh lala! Where can I find a schematic of this?

I can't recommend any specific treatment, but if you start from a search "how do tristate busses work" that might get you the right material. An image search is often a good way to find an article with illustrations.

BigEd
Which of those methods is more effective? Thank you so much for the help!

Oh, so you would have something like this?

Not entirely unlike that, but by using AND gates, you're saying you want to squash a value to zero.

Have a look for images using and-or-invert gates.

Or perhaps have a look at this
https://cs.wellesley.edu/~cs240/spring1 ... cuits.html

In electronics, it's not unusual to see tristate busses: each wire of the bus can be driven high, driven low, or not driven, by each of the potential drivers. It's very compact, because the bus serves all the clients with just 8 wires.

But sometimes you don't have the option of not-driving - it's true inside many FPGAs, and it may be true in minecraft. In that case you'd use combinatorial multiplexing, where a driver not-driving means driving a zero, and then all driver outputs can be ORed together.

I wonder if this picture will help:
http://patentimages.storage.googleapis. ... D00002.png

But BigEd, could that work for redirecting the arguments to the appropriate places or is there a more effective way?

I'm not happy with all this talk of the arguments! I wonder if we're talking about the same thing. In the 6502 we have a one-byte opcode, and optionally one or two one-byte operands. All of these are read from memory and come into the chip on the databus. So it is necessary for the databus to be able to bring its value to many internal locations: the IR, and A, X, and Y, and also the ALU input, and so on.

Do you mean something different by arguments? Can you elaborate?

Certainly in the inside of a micro there are lots of wires, and if you don't have the luxury of tristate logic then you'll have even more wires. In a minecraft context that is sure to be a great deal of communication construction. But that's how it is - there's computation, and there's communication. There's a lot more to a micro than an ALU.

That's what I meant, operands/parameters/arguments or whatever.

BigEd,
"So it is necessary for the databus to be able to bring its value to many internal locations: the IR, and A, X, and Y, and also the ALU input, and so on", what I needed was a way to choose where to bring the databus, the last thing I asked was if that thingy could work as in, choosing where to bring the arguments.

I think you're on the right lines: you have brought your operand bus to all the receivers, by running it past them all. And you've got some control mechanism to arrange that different receivers can use or not use the operand, according to what the opcode said. But I think in detail what you've got doesn't work.

Let's say you've got A, X, Y and ALU-input-A as your possible receivers. They all have access to the operand. But, most of the time they need to ignore it, and if any of them do need to use it, probably only one of them does. More importantly, A, X and Y also need to be able to get their input from an ALU output.

So perhaps you need to look at this not as a what-do-I-do-with-this-bus, instead look at the question from the receiver perspective. If you're the X register, what might you do?
- keep my value
- get the value of the databus (the operand)
- get the value of A
- get the value of the output of the ALU

So you need control signals for each of these cases. Looking at the visual 6502 you'll see there are about 43 control signals running into the datapath, called dpcNN_something.
http://visual6502.org/JSSim/nodenames.js

For each sender, you need an enable signal, and for each receiver you need one or more selector signals.

As you'll see in Donald's diagram, the 6502 has three internal busses, with two interchanges, to allow for all the necessary traffic routing.

Thank you so much, BigEd! That helped A LOT. Sorry if I annoyed you a bit by asking so many questions but this is the only forum in which the smart CPU guys are, and with a 6502.

Glad I could help!

LBSC, don't ever be afraid to ask as many questions as you need to ask. It's one of the best ways to learn. Books can be good to learn from, but you can't have an ongoing discussion with a book in order to clarify an idea or concept. You're taking the answers to your questions on board, and using that new information in follow up questions, this is exactly how questions should work, and is not something I would consider to by annoying.