LDA #$00
STA  $5005      ;IMR - Disable IRQs
LDA #$BA
STA  $5002      ;CRA - Disable TRxA; MRA -> MR0
LDA #$66
STA  $5001      ;CSA - Select 115,200 baud
LDA #%01001100
STA  $5000      ;MR0 - Rx Watchdog off, RxINT=16B, TxINT=16B, FIFOs to 16B, Baudrate table: Extended II
LDA #%01010011
STA  $5000      ;MR1 - Rx RTS control off, RxINT=16B, error-per-character, no parity, 8bits/char
LDA #%00000111
STA  $5000      ;MR2 - Normal channel mode, no Tx RTS or CTS control, 1.000 stop bit
LDA #%00110000
STA  $5004      ;ACR - BRG=0, C/T as counter from XTAL/16, no change IRQs
LDA #$05
STA  $5002      ;CRA - enable TRxA

LDX #$52        ;"R"

  LoopTop:
LDA  $5001      ;Get DUART.SRA
AND #$00000100  ;Mask out all but the TxRDY bit
BEQ LoopTop     ;If not set, then the FIFO is full
STX  $5003      ;If we get here, then there is space in the FIFO. Put one in.
BRA LoopTop     ;Loop

INTERUPT1   LDA   Via1IFR   ;Get IRQ flag register, xfer irq bit to n flag (4)
               BPL   REGEXT1   ;if set, 6522 caused irq,(do not branch) (2/3) (7 clock cycles to exit - take branch)
               BIT   #%00100000   ;check T2 interrupt bit (2)
               BNE   DECMSD   ;If active, handle T2 timer (MS delay) (2/3)
               BIT #%01000000   ;check T1 interrupt bit (2)
               BNE   INCRTC   ;If active, handle T1 timer (RTC) (2/3)
               STA   STVVAL   ;Save in status before exit (3)
               BRA REGEXT1   ;branch to next IRQ source, exit (3)