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kakemoms
PostPosted: Tue May 09, 2017 3:13 am 
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Hi

If I run this loop the core crashes when it exits the loop:

Code:

tag
        text ' the supervixen               has started!  '

start
        LDX     #42
loop
        LDA     tag,X ; Copy text buffer
        STA     $2000,X
        DEX
        BNE     loop
end
        NOP
        JMP     end


It happends every time with both the extended 65C02 and Arlets original. Can you check if this is generally true or if its only in the Active-HDL simulator?

I also had problems with stopping the core with RDY, so used the workaround with extending the Clock cycle that seems to work fine (same as used by the SuperCPU of C64).
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BigEd
PostPosted: Tue May 09, 2017 11:34 am 
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I've checked on FPGA, and the core is working as expected - I put an INC $3000 in the JMP loop so I could see if it had gone around. (I needed that because I have to reset the 6502 to get out of the JMP loop.)

(Might be worth noting: you're not copying the zeroth element of the string, so need to tweak your loop a bit.)

(Might be worth starting a new thread for a support problem or bug report, rather than using an announcement thread. I read all new posts in every part of this forum, as I think do many others here, so don't worry about not being seen.)
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kakemoms
PostPosted: Tue May 09, 2017 2:09 pm 
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BigEd wrote:
I've checked on FPGA, and the core is working as expected - I put an INC $3000 in the JMP loop so I could see if it had gone around. (I needed that because I have to reset the 6502 to get out of the JMP loop.)

(Might be worth noting: you're not copying the zeroth element of the string, so need to tweak your loop a bit.)

(Might be worth starting a new thread for a support problem or bug report, rather than using an announcement thread. I read all new posts in every part of this forum, as I think do many others here, so don't worry about not being seen.)


Ok, sorry I will make it a new tread.

Edit: I made the 65C02 run in the Lattice MachXO3. It seems to be able to run above 33MHz, but currently I have limited it to 22MHz. Note that you can get the MachXO3 for around 2-4$/pc.


Last edited by kakemoms on Mon May 15, 2017 8:44 pm, edited 1 time in total.

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barrym95838
PostPosted: Wed May 10, 2017 4:09 pm 
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BigEd wrote:
... I read all new posts in every part of this forum, as I think do many others here, so don't worry about not being seen ...

Yes, bookmarked over here as well. It's a very convenient feature.

search.php?search_id=unreadposts

Mike B.
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rwiker
PostPosted: Wed Sep 13, 2017 8:41 pm 
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Today I finally got a Xilinx installation working under Linux (actually, under two Linuxes - Ubuntu 16.04 and Centos 6.10 running in a Docker container... the setup is frankly bizarre, but it should be possible to make it somewhat less so).

I then took enso's build setup for CHOCHI (45_004) and modified it to use the 65c02 core; I also reduced the clock frequency to 40MHz, as I had some problems that I thought might be caused by running at too high frequency.

I'm a complete beginner at this, so even these small steps have been quite rewarding :-)
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Windfall
PostPosted: Thu Sep 14, 2017 9:33 pm 
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Just as a complete and utter 'aside', I recently experimented a bit with this core and have it running at 250 MHz on http://www.terasic.com.tw/cgi-bin/page/archive.pl?No=733 in http://www.zeridajh.org/hardware/soft6502secondprocessor/index.htm, whereas M65C02 could 'only' be pushed to 140 MHz (apparently the microcode is hurting performance in this context).
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Dr Jefyll
PostPosted: Thu Sep 14, 2017 11:58 pm 
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Thanks for posting! It's useful to have these data points.

Windfall wrote:
(apparently the microcode is hurting performance in this context).
Hmm.. a slightly hasty choice of words, perhaps. It's fair to say clock speed was affected. But performance is more complex to evaluate. The M65C02 has a far more powerful instruction set than the 65C02, and (except in simple, 8-bit applications) its performance may exceed that of the 'C02, clock rates notwithstanding.

Edit: oops, the link and the comment aren't directly pertinent. It's the M65C02A I was thinking of.

_________________
In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html


Last edited by Dr Jefyll on Fri Sep 15, 2017 12:28 am, edited 1 time in total.

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Windfall
PostPosted: Fri Sep 15, 2017 12:10 am 
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Dr Jefyll wrote:
The M65C02 has a far more powerful instruction set than the 65C02, and (except in simple, 8-bit applications) its performance may exceed that of the 'C02, clock rates notwithstanding.


I'm not sure what you're talking about here. Arlet's (the 65C02 version) and MichaelM's cores have the same instruction set. Former uses the same number of cycles as the original, latter uses a few less here and there. Otherwise, there are no differences.

So please elaborate.
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barrym95838
PostPosted: Fri Sep 15, 2017 12:18 am 
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From Michael's post at Jeff's link:
Quote:
My second goal was to reduce the size of the core's logic so that I could include support for additional addressing modes, 16-bit operations, and make the architecture more compatible with high level languages such as C and Pascal. A sub-goal was to maintain seamless compatibility with the W65C02S in order to execute 6502/65C02 code at any time. This goal has been met by a redesign of the ALU and address generation logic of the M65C02 core. Additional controls and multiplexers were provided in both of these components so that several new addressing modes could be added in a backwardly-compatible manner with the 6502/65C02. The redesign of the ALU allowed the M65C02A ALU to be enhanced to support single cycle 16-bit logic, shift/rotate, and arithmetic operations in virtually the same footprint as the ALU for the 8-bit M65C02 ALU with the limitation that BCD addition/subtraction operations are limited to 8 bits.

My third goal was to provide instructions to directly support a DTC/ITC FORTH VM. The M65C02A provides a number of instructions that allow the implementation of both DTC and ITC versions of the FORTH VM. The instructions are supported by the addition of a module in the M65C02A core that provides the Interpretive Pointer (IP) and the Working (W) register. It also supports the 16-bit operations on these registers which are needed to use them effectively. A new IP-relative addressing mode was added and supported by three instructions: LDA, ADC, and STA. These instructions allow speedier access to literals, constants, and variables. In addition, the IP-relative ADC instruction can be used to implement efficiently relative branches.


Mike B.

[Edit: Oh, wait ... that's the M65C02A ... nevermind!]
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Dr Jefyll
PostPosted: Fri Sep 15, 2017 12:25 am 
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barrym95838 wrote:
[Edit: Oh, wait ... that's the M65C02A ... nevermind!]

Yes, apologies -- I made the same mistake, mixing up the M65C02 and the M65C02A. Gotta watch those suffixes! :oops:

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In 1988 my 65C02 got six new registers and 44 new full-speed instructions!
https://laughtonelectronics.com/Arcana/ ... mmary.html
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Tor
PostPosted: Fri Sep 15, 2017 6:16 am 
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250MHz - that's something. Then I had a look at the price tag of the fpga board.. $15k! :)
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Windfall
PostPosted: Fri Sep 15, 2017 8:42 am 
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Tor wrote:
250MHz - that's something. Then I had a look at the price tag of the fpga board.. $15k! :)


Yes. Let's just say that both the speed and the board are quite something ... :D

It's a nice board. Actually, mine (brand new but cheaply bought) is a special case, with bigger FPGAs than the regular board, namely these :

https://www.digikey.nl/product-detail/en/altera/5SGXEABN2F45C2N/5SGXEABN2F45C2N-ND/4160107

But it lacks the QDR and Mosys SRAM (although the internal memory of 60+ Mb each is plenty of playing material).
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BigEd
PostPosted: Fri Sep 15, 2017 9:42 am 
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That's a huge FPGA - any idea how many 6502 cores it could fit?
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Windfall
PostPosted: Fri Sep 15, 2017 9:57 am 
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BigEd wrote:
That's a huge FPGA - any idea how many 6502 cores it could fit?


In cells (ALMs), something near 1000.

I could fit around 100 of my 6502 Second Processors in there (limited by internal memory rather than cells).

And, of course, there's two of them (FPGAs), so if you're really going crazy, there's some more room yet ...
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BigEd
PostPosted: Fri Sep 15, 2017 10:31 am 
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So in some handwavey and incorrect sense that's 500GHz of 6502 power for $15k...
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