FT600 timing diagram. In my design this should connect the AL460 FIFO to the USB "backbone/nerve-chord). I was thinking TUSBxxx (?) from texas instruments, as the host controller/chipset, to run the backbone. Can buy the card with two (or three?) USB 3.0 ports, and a PCIe connection. I think "Sam"--my AI robot-- can just use a desktop computer and/or laptop (preferably a light one, in his stomach?) with the PCIe card plugged in, for a brain. Also, I have a sans digital RAID array (presently being finicky in its "recognizing drives in bay"?), and 2 QTY 3 terabyte (toshiba? panasonic?) HDDs. Plenty of space for visual memory.
TXE pin says when FT600 has some of its 4KB (8KB?) FIFO is awaiting info from the AL460-FIFO. Not to be confused; on FIFO is a small buffer, in the FT600 awaiting USB transfer, and the other is the big FIFO. Documents can get confusing, when reading them. Who reads? who writes? who buffers in what FIFO? It pays to be specific.
I only want to write to the FT600 FIFO buffers, for output to the USB. So, the other diagram is unecessary (included below, for completeness.). Note, in the mode I want to use it, OE stay low, throughout. And so, I just need to find something to pull WE low, after TX has pulled low.
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