To me, the critical delay path now looks like this:
Phase counter > Microcode ROMs > register read decoder + register read > ALU > flag evaluation logic + ROM > SR.

For functional testing, feeding the CPU external data bus with a DIP switch (plus pullup resistors) would be nice for a start.
If a permanent $A9 on the data bus loads the accumulator with $A9 while incrementing the PC,
quite some part of the CPU seems to work as intended...

BTW: peeling most of the bugs out of the M02 microcode took about 3 months.

Yes of course. That's what I have been doing so far. Everything works with manual control. Including phase control, IR load, PC++, register loads, mem read/write, (ALU) SHL, etc.
Breadboard wiring and testing so far: 35h

It was nice that my timing/clock design worked on first try. Phase control/IR load/PC++ in Phase0 before actual operations was one of my design goals. Whether everything continues to work with the actual control logic... that remains to be seen...

Axel.

There is no new delay due to Flag ROM, because between "ALU output"/"memory output"/"memory input" etc AND phase end there must be a long delay. RAM write has 85ns max delay while ROM read has 70ns. So if Flags ROM+logic is below 85ns it is not limiting my second time period.
If you take a look the timing diagram, thats the time period between "IR latch" and "Register latches".
Dropping delays of logic chips out of the equation the max frequency is 5.9MHz. One instruction phase is one clock cycle in this state machine.

I would consider 1MHz a victory and probably won't go much faster than that (well... we'll see about that... )

Axel.

Microcode ROMs in and testing:

LDA #$62
ADC #$13
STA $0008

$0008=


Looks like I may call this a computer

Axel.

Pull back! I'd love to see a photo of the whole thing powered on.

Here you go:


Top to bottom:
Databus value
PC
AR (control signal logic on right)
Membus multiplexer (Run/Prog mode)
RAM (and Prog mode address+value)
IR (control signal logic on right)
Phase counter + microcode ROMs
Full address + substraction (=XORs) and reset
A and T regs
Clock signal generation + manual clock/555 oscillator
Flag generator + Zero flag calculator + SR

Well done!

Thanks. I'm starting to route the first version of pcb soon. It seems that everything on board works as planned.
Btw: what happens in real 6502 when reset is released in the middle of clock pulse? In my case it starts to execute cleared IR (opcode $00) which happens to be a valid instruction. That needs to be resolved somehow...

Axel.

It does not matter what part of the clock cycle you're in when you release RST\. It always does the same thing, regardless.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

A huge amount of work. Well done! Nice labels!

9.7x8"
douple side
few cups of coffee...

Ax2013 please verify the actual case dimensions of your ICs. The ones with 14 pin (U67/68) might actually be larger so that the space between them is nearly zero and then there is no room left for what I assume are decoupling Cs. If you will use sockets the space between them may be sufficient for small axial type Cs, but w/o sockets ...

Thanks for the heads-up. There is enough space - actually I've added 25mils extra between decoupling caps and ICs. The space between ICs is about twice of a ceramic cap width.

Axel.

Amazing progress! I really like the way the datapath is laid out. One question: how does your microcode handle writing PC to the stack since both PC and SP connect directly to the address bus?

_________________
C74-6502 Website: https://c74project.com

Thanks Drass!
PC address to stack can be written through T reg. (HI/LO Addressbus gateway to left ALUbus - see the logical diagram few posts earlier).

Axel.