I'm working on a new design for a 65C02 system in which I want to use a PIC18F part to load the SRAM while the 65C02 is halted and has BE held low.

My guess is that PHI2 will continue to oscilate while the address, data and RWB are made high impedance. Would I be right in thinking that I would need to change my /OE and /WE control signals for the SRAM to be more like this:

/OE = !((RDY & PHI2 | CLK) & RWB)
/WE = !((RDY & PHI1 | CLK) & !RWB)

Where CLK is an active high signal generated from the PIC when it wants to read or write data. (The pic will also generate data, address and RWB signals when it has control of the buses).

_________________
Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

Hi,

yes you are right to assume that Phi2 keeps on running even while
RDY is set low. The address and data lines, however, are not(!) made
high impedance.

The purpose of the RDY line is to keep the CPU waiting for slow
memory or I/O. So the address lines (and data lines in case of write)
keep their valid state.

I have a schematics in the works where a second CPU takes over the
bus from the main CPU, holding the main CPU via RDY, and I have
to decouple the CPU lines with '245 drivers.

Oh, sorry, I see that you are using a variant with a BE line - I assume
that would be possible too instead of the '245, but I have no
experience with it (still only using what's available to me - R65C02 -
that do not have this line).

BTW: anyone know a good source for WDC chips in Germany?

André

I haven't been able to put the time into figuring out the best way to do this, but the logic:
/OE = !((RDY & PHI2 | CLK) & RWB)
/WE = !((RDY & PHI1 | CLK) & !RWB)
seems a lot more complex than it needs to be, which will reduce your maximum useable clock speed. Since you just want to load the BIOS into RAM before releasing the processor, why not inhibit the clock from reaching the processor at all during the RAM-loading process, and use tri-state buffers between the uP and the PIC. Then they won't load the lines or produce additional delays after the processor is up and running. (I haven't looked at this stuff in a long time, so I hope I'm not sticking my foot in my mouth.) The point is to have a minimum number of gates' delay between especially phase 2 and the selects on RAM and other ICs. I usually tie OE\ to ground. Output is automatically disabled when the CS is false or WE\ is low.