Thanks -- I overlooked that until now.

Just a suggestion, but for the next draft of the schematic I think you can shrink the chip count quite considerably. I see many instances where a pair of '173 4-bit registers are used to form an 8-bit register, like this:But almost the same function can be achieved by a single 74xx377 -- in each instance, two chips can be replaced by one. The only difference is reset, which isn't available on a '377. But I don't see any need to reset X Y A PC etc -- a real 6502 doesn't reset those registers. Am I missing something?

cheers
Jeff

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Hello,
Thanks for the message. I built the breadboard prototype using 173s and I didn't think that the amount of chips would be an issue. Now when I see the complete set of registers on screen I fully agree. I would like to see a single 8-bit register chip instead of two chips.
It might also be an issue if PCB size becomes too large and beyond economical prototyping. (The max PCB size of my CNC is eurocard 10x16 so I need to order this one).

However 377 does not have 3-state output so 377+245 is still two chips. IR is the only register I could replace by 377. However I would like to see a valid opcode in IR on reset hence I set the IR to zero.

I'm not aware of a single 8-bit register with synchronized clock and 3-state output. 373 has 3-state output but it is not synchronized. 2x8 datapins, OE, E, CLK, VCC, GND is 21 pins total. I think there aren't such a chip available (at least as TTL), but I stand corrected.

Probably the most optimal way to build this is to use 373s. Just that my design is based on a common clock and register based Enable control signal.

Axel.

What about the '574? 8-bit, positive edge triggered register with 3-state outputs. Only thing missing is an async reset, but you can simulate that by gating in the input bus whilst driving it low somehow - on my RAMON5 processor I do this using the '382 ALU's "clear" function, which outputs all zeroes regardless of input.

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Hello, thanks but 574 does not have a Latch enable. I have common clock and target register is selected by latch enable signal. Missing reset is not an issue, but since there is one I have utilized it.
374 and 574 would be a good choice otherwice.

Axel.

Whats about a 74LS498 ? Probably hard to find and only LS AFAIK.

Hello,
Thanks. Interesting chip. That one contains required functions but unfortunately so rare. Never looked specs until now. Nice rotate feature built in!

Axel.

There might be other approaches for building a more compact ALU:
http://6502.org/users/dieter/a1/a1_6.htm
http://6502.org/users/dieter/a7/a7_1.htm

Unfortunately, 74181 and 74381 seem to be out of production now.

It's possible to build an ALU from EPROMs:
http://6502.org/users/dieter/a1/a1_2.htm


74ALS569 4 Bit up\down counter with three state outputs looks interesting,
but it's exotic, it's expensive, and it's hard to say how long it will stay in production.
(Price tends to drop when buying a lot of ICs of the same type.)
http://www.ti.com/lit/ds/symlink/sn74als569a.pdf

Hello,
Yes, there are many options. I didn't wanted to use "a ready made" 181 but rather used basic and generally available stuff instead. Eprom approach is interesting but I already have done SW based 6502. Now wanted to build pure hw based version. Well... my control logic has three eproms anyway... Also it would be so much easier to use GAL/PAL/PLD chips for many operations. That would reduce the number of chips pretty much.

Axel.

Well, looks like buying GALs etc. in DIP package might be getting a bit difficult in the future.

There is a trick for using EPROMs as PLDs... slow PLDs of course:
http://6502.org/users/dieter/a1/a1_1.htm

Point is, that there is a CPU which was built with 12 EPROMs:
http://2x-1.net/ob/gray1/

Nice design!

I have drown everything else except Flag control (PDF as attachment). I have run out of ideas! Latching just the flags is simple but instructions like BIT, PHP and PLP are more complex to implement. ROM based lookuptable would be a simple solution (like in ttlworks' TTL 6502). Also GAL would be an easy choice since it could handle maskable latching, rotating, input selection etc. very easily.

Axel.

Since the flags NVZC have to be tested for the conditional branches, you probably don't want to use a latch
with three state outputs for building the status register.

BTW: testing NVZC flags with a 74151 or such controlled by Bit 7..5 of the OpCode probably might save
some address lines on those microcode EPROMs.

When building the status register with a 4 Bit or 8 Bit register instead of individual 7474 flipflops,
I think that quite a few multiplexers would have to be at the inputs of that register...

Some thoughts on implementing the V flag evaluation are here:
http://6502.org/users/dieter/v_flag/v_3.htm

Yep, I have done V flag generation already. The only part missing is SR register implementation. Depending on register type (7474 or D regs) it would require a whole punch of logic around. I drew that on paper and it is no go.
Placing 4-bit SR reg next to A register and using ROM might be the best option. I didn't want to use ROM there but that is the best solution I have now. All of the SR stuff should be able to do with this setup:

A0: Databus D4 IN (or D0 maintaining the original flag placement)
A1: Databus D5 IN (or D1 maintaining the original flag placement)
A2: Databus D6 IN
A3: Databus D7 IN
A4: Current C IN
A5: Current Z IN
A6: Current V IN
A7: Current N IN
A8: Command: LatchNZ (New Z in and Databus D7; the rest as is)
A9: Command: LatchNZC (New ZC in and Databus D7; the rest as is)
A10: Command: LatchNZCV (New ZCV in and Databus D7)
A11: Command: PLP (Load all from Databus)
A12: Command: BIT (Load D6 and D7 from Databus; the rest as is)
A13: New C IN
A14: New V IN
A15: New Z IN

RC1 of the schematic. If everything works on breadboard this is very near what I'm going to route.
Made a draft component placement to see how big the PCB will be. It is only 230x250mm. It is well below economical PCB prototype size. There is even space for bus leds!
remark: there is now RAM/ROM/IO on the mainboard

Axel.

SR implementation sure would require a lot of logic, especially when using a D register instead of 7474.
IMHO using 74151 multiplexers at the input of the SR would simplify the logic required:
http://forum.6502.org/download/file.php?id=3282&mode=view&sid=7c96e3ac5e654ccda2484af48fa02d40

Using a ROM would be the most simple solution...
but depending on the ROM read access time, this would limit the speed of the CPU.

;---

About the PCB:

Looks like you are using 4 Bit adders and 4 Bit registers, so there might be a chance to go with
two identical 4 Bit PCBs for the CPU "mill" to have 8 Bit.
(As for the year 2017, the 74LS243 4 Bit bus transceiver still seems to be in production... yet.)

SR and flag evaluation won't be on those two PCBs, of course.

For instance, this 32 Bit dinosaur used two identical PCBs which contained ALU and registers for 16 Bit.

Hello,
Having separate register PCBs for registers was my original plan, but changed my mind while doing breadboard testing. I consider one PCB better choice to continue in this case. Multiple PCBs would give some flexibility in design process but I try to do enough functional testing on breadboard.
Using ROMs in SR logic does not limit max speed more - those same ROMs are being used in control logic already so the limitation exists already.
I hope I could do actual functional testing with state machine in the near future and then able to find out whether this is just a pile of wires or actual computer project...

Axel.