I've been working on my processor quite a bit over the last couple days and started implementing the ASL and LSR opcodes using absolute addressing mode. I observed that for other instructions that use the ALU (e.g., ADC) that mode takes 4 clock cycles to complete. Assuming that ASL and LSR are using the ALU as well, it seems odd to me that those operations would take longer.

Is there a reason it takes an extra two clock cycles for those two instructions to execute relative to the others? Thanks.

I may have answered my own question - the block diagram for the processor shows the ALU connected to an adder for some reason. Perhaps the ALU needed to use that to add something to the shifted result and then another clock cycle to register it back in the processor?

I think at least part of your answer lies in the '816 data sheet:


It takes an extra cycle to do the operation and another to do the write-back since the result does not go in a processor register. Note that "data high" in the table (in the column second from the right edge) only applies to the '816 and only when you have its accumulator in 16-bit mode, and does not apply to the '02.

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Right. ADC requires just a single access to memory at the specified address.

In contrast, ASL LSR ROL ROR INC and DEC are Read-Modify-Write instructions. They conclude by taking what's at the specified address, altering it, and putting it back. The "alter it and put it back" is what adds the two extra cycles. You can see this in the chart excerpt Garth posted.

(ADC operates on the Accumulator -- an internal register. The "alter it and put it back" doesn't require access to memory.)

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Yeah, I completely missed that in the instruction description - for some reason it completely escaped me that I needed to do something with the result. I suppose that's what I deserve working on code at 3:00 AM. I need to go back and modify some of my design now.