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BigDumbDinosaur
PostPosted: Wed Jul 26, 2017 5:26 pm 
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DerTrueForce wrote:
I haven't built the kit yet; that'll have to come a little later, as I'm not at home right now, and I didn't bring my soldering iron. I don't want to set off the fire alarm with the flux smoke. Can't afford the fine.

Just tell them you accidentally burned your toast while eat breakfast. :D

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DerTrueForce
PostPosted: Fri Jul 28, 2017 3:36 am 
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I have gotten home and built the probe. I have tested it, and it works.
What should I be probing? /CS and the TxD pin on the channel I'm using?

EDIT: And while I think of it, there was somebody else who was having trouble with his 28L92. I'm using a 'C02 like him. Could I be running into a similar problem, do you think?
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BigDumbDinosaur
PostPosted: Fri Jul 28, 2017 7:28 am 
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DerTrueForce wrote:
I have gotten home and built the probe. I have tested it, and it works.
What should I be probing? /CS and the TxD pin on the channel I'm using?

Test /CS on the DUART by doing on a read on the DUART's base address, which will read MR. When quiescent, /CS should be high. Reading from the DUART should cause /CS to briefly go low. If you see that then your chip select logic is correct.

Next, perform the same test, but with the probe on the DUART's /RD signal. It should be high when quiescent and briefly go low during the read.

Quote:
EDIT: And while I think of it, there was somebody else who was having trouble with his 28L92. I'm using a 'C02 like him. Could I be running into a similar problem, do you think?

You may be thinking of this post. At first blush, it appears the 65C02 may have a problem with doing spurious reads while processing indexed instructions. If so, an accidental read could touch the DUART's mode register and trip you up when trying to configure the device. We're not sure at this point what is going on, as Drass' circuit doesn't qualify /OE with Ø2, which in itself creates the potential for spurious reads.

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DerTrueForce
PostPosted: Sat Sep 23, 2017 12:02 am 
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I have just gotten channel A working with linear initialisation and polled I/O using the following code:
Code:
LDA #$00
STA  $5005      ;IMR - Disable IRQs
LDA #$BA
STA  $5002      ;CRA - Disable TRxA; MRA -> MR0
LDA #$66
STA  $5001      ;CSA - Select 115,200 baud
LDA #%01001100
STA  $5000      ;MR0 - Rx Watchdog off, RxINT=16B, TxINT=16B, FIFOs to 16B, Baudrate table: Extended II
LDA #%01010011
STA  $5000      ;MR1 - Rx RTS control off, RxINT=16B, error-per-character, no parity, 8bits/char
LDA #%00000111
STA  $5000      ;MR2 - Normal channel mode, no Tx RTS or CTS control, 1.000 stop bit
LDA #%00110000
STA  $5004      ;ACR - BRG=0, C/T as counter from XTAL/16, no change IRQs
LDA #$05
STA  $5002      ;CRA - enable TRxA

LDX #$52        ;"R"

  LoopTop:
LDA  $5001      ;Get DUART.SRA
AND #$00000100  ;Mask out all but the TxRDY bit
BEQ LoopTop     ;If not set, then the FIFO is full
STX  $5003      ;If we get here, then there is space in the FIFO. Put one in.
BRA LoopTop     ;Loop
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BigDumbDinosaur
PostPosted: Sat Sep 23, 2017 12:40 am 
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DerTrueForce wrote:
I have just gotten channel A working with linear initialisation and polled I/O using the following code:
Code:
LoopTop:
LDA  $5001      ;Get DUART.SRA
AND #$00000100  ;Mask out all but the TxRDY bit
BEQ LoopTop     ;If not set, then the FIFO is full
STX  $5003      ;If we get here, then there is space in the FIFO. Put one in.
BRA LoopTop     ;Loop

The above could be more efficiently written as:

Code:
         lda #%00000100        ;TxRDY test mask
;
LoopTop  bit $5001             ;TxD FIFO full?
         beq LoopTop           ;yes
;
         stx $5003             ;no, write datum &...
         bra LoopTop           ;loop


EDIT: "BRA LoopTop" was erroneously typed as "BRA LopTop". Apparently I...er...lopped off part of LoopTop. :D

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Last edited by BigDumbDinosaur on Sat Sep 23, 2017 11:34 pm, edited 1 time in total.

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GARTHWILSON
PostPosted: Sat Sep 23, 2017 1:06 am 
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Good catch. Also, the LDA #0, STA $5005 at the top can be shortened to STZ $5005.

It always feels good to get something working! :D

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DerTrueForce
PostPosted: Sat Sep 23, 2017 2:17 am 
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Oh, that is shorter. I'm fairly new at this, so I've got lots of room to improve.
It does indeed feel good to get things working. Now I should figure out why BDDs code doesn't work for me.
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BigDumbDinosaur
PostPosted: Sat Sep 23, 2017 2:26 pm 
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DerTrueForce wrote:
Oh, that is shorter. I'm fairly new at this, so I've got lots of room to improve.
It does indeed feel good to get things working. Now I should figure out why BDDs code doesn't work for me.

What about it isn't working?

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floobydust
PostPosted: Sat Sep 23, 2017 2:43 pm 
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BigDumbDinosaur wrote:
DerTrueForce wrote:
Oh, that is shorter. I'm fairly new at this, so I've got lots of room to improve.
It does indeed feel good to get things working. Now I should figure out why BDDs code doesn't work for me.

What about it isn't working?


If he entered it verbatim, it won't work. You used the same label as "LoopTop" but the final branch shows as "LopTop". Granted, one would expect an error on assembly for the "LopTop" label unless it's somewhere else in the code. Other than that I don't see why it wouldn't work.

When servicing an interrupt and polling a chip that can have multiple interrupt sources, I would prefer to load the A reg with the status register and use BIT to test for specific bits being active. Below is a snippet for handling the timers on a 6522 VIA:

Code:
INTERUPT1   LDA   Via1IFR   ;Get IRQ flag register, xfer irq bit to n flag (4)
               BPL   REGEXT1   ;if set, 6522 caused irq,(do not branch) (2/3) (7 clock cycles to exit - take branch)
               BIT   #%00100000   ;check T2 interrupt bit (2)
               BNE   DECMSD   ;If active, handle T2 timer (MS delay) (2/3)
               BIT #%01000000   ;check T1 interrupt bit (2)
               BNE   INCRTC   ;If active, handle T1 timer (RTC) (2/3)
               STA   STVVAL   ;Save in status before exit (3)
               BRA REGEXT1   ;branch to next IRQ source, exit (3)

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DerTrueForce
PostPosted: Sat Sep 23, 2017 10:38 pm 
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Sorry, BDD, I was referring to the extract of POCs firmware that you sent me a while back. That's what doesn't work for me. I suspect the indexed write may be to blame. One of these days I'll single-cycle through an indexed write and find out just how the 'C02 behaves when it does one of those.
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BigDumbDinosaur
PostPosted: Sat Sep 23, 2017 11:35 pm 
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floobydust wrote:
If he entered it verbatim, it won't work. You used the same label as "LoopTop" but the final branch shows as "LopTop". Granted, one would expect an error on assembly for the "LopTop" label unless it's somewhere else in the code. Other than that I don't see why it wouldn't work.

Fixed.

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BigDumbDinosaur
PostPosted: Sat Sep 23, 2017 11:49 pm 
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DerTrueForce wrote:
Sorry, BDD, I was referring to the extract of POCs firmware that you sent me a while back. That's what doesn't work for me. I suspect the indexed write may be to blame. One of these days I'll single-cycle through an indexed write and find out just how the 'C02 behaves when it does one of those.

There is some evidence that the 'C02 does a dummy read of the addressed location before writing when using absolute index addressing. During setup of any of the 26* or 28* NXP UARTs, if the addressed register is MR (MR0, MR1 or MR2), the dummy read will be "destructive," in that the read will increment the MR pointer. For example, if an earlier instruction set MR to MR1 in preparation for writing a setup value to MR1, the dummy read will advance the MR pointer to MR2 and the write will instead touch MR2.

See this, in which this anomaly was brought up. Jeff suggested a bit of a code hack involving a forced crossing of a page boundary that apparently avoids the problem. The problem won't occur in a properly designed 65C816 system due to the address qualification provided by the VDA and VPA outputs.

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