I concur with Garth's diagnosis. I'm running 12ns RAM in my POC V1.1 unit and have no problems with any clock speed from 1 MHz to 12.5 MHz (and will boot at 15 MHz with a 45ns OTP ROM).

POC V2 uses the same SRAM Garth uses in his 4MB DIMM. It works fine over the same speed range. This is likely a peculiarity of Alliance's SRAM.

Also, what about that '688?

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Speaking of the '688... I attempted a quick and dirty layout with a slightly different architecture (64K RAM + ClockGen/Loader) and adding address select jumpers to the '688 was probably the easiest part of this 'test' layout.

I believe having the ability to change the I/O address page would be an important feature.

Cheerful regards, Mike

@Michael: nice! Is that the Kicad feature that allows you to show the board in 3d?

Be careful that the VCC line between VCC and /RST is actually not VCC but the Z80 /M1 signal. This signal is needed to qualify I/O ops vs interrupt ack. I tie that to high/VCC on my non-Z80 CPU boards.

I generally gate RAM OE and WR signals to Phi2 to fully qualify them. That unfortunately adds a '00 to my design.

If you are using other RC2014 memory boards (presumably ROM), you'll want to invert the A15 signal. My long winded blog article have those details http://ancientcomputing.blogspot.com/2017/05/a-6502-cpu-for-rc2014-part-1.html. If you are going full native 6502, that is unneeded.

I am also now using pin 39 of the RC2014 bus for the R/W signal from the 6502. This is primarily for driving 65xx/68xx-style peripherals that need a Phi2 pre-rising edge setup time for control signals. So the 6522 board uses that as well as my upcoming 6551 board.

Finally, as I suggested to CommodoreJohn, if you looking for versatility for the I/O port mapping, consider putting it and the associated circuitry on its own plug-in board. This is really more aligned with the RC2014 philosophy (which I've freely violated ) of segmenting distinct sub-functionalities into their own physical "modules".

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Blog: http://ancientcomputing.blogspot.com/
GitHub: https://github.com/ancientcomputing

No, that output is from DipTrace.

Oops! Thank you. I missed that.

Yes, I understand that's necessary for non-65xx peripherals.

I did read your articles. Very nice write up. Your solutions for overcoming the hurdles imposed by this particular architecture and bus and for using some of the RC2014 peripheral boards were/are very elegant.

I have relatively simple "loader" methods/designs for 65C02 and CDP1802 (Z80 coming soon) so I don't see any advantage using ROM and I shouldn't have to mess with the A15 address line. Also, I suspect that placing a 64K or 128K RAM chip on each CPU board will reduce the need to add missing signals to the bus.

Then I will use pin 39 for that signal on my layout, too.

Yes, I noticed the violations (grin). Most of Grant Searle's "Minimum Z80" computer was broken down into modules on a bus and you've re-integrated the separate clock and decoder modules into your 65C02 board design (grin).

I admit it's tempting to put a whole 4-chip Serial 64K 65C02 computer on a single card (see below) but I'm not sure I could route it...

Cheerful regards, Mike

@Mike: looking at your edited post with the PCB layout, it looks you're breaking the other RC2014 rule: no fancy modern ICs like that PIC

For folks who don't want to layout/design your own 6502 boards for the RC2014, I got 10 more of my RevB boards in on Tindie.

The main differences of Rev B versus the original are (a) routing R/W to pin 39 of the bus for use with the 6522, 6551 and 6532 boards, (b) an option to invert A14 so that you can use the RC2014 64KB RAM board configured for 48KB (along with the Pageable ROM board configured for 16KB).

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Blog: http://ancientcomputing.blogspot.com/
GitHub: https://github.com/ancientcomputing

Didn't Semach(the designer of the RC2014) blow that one wide open with the Pi Zero Serial Terminal module?

Huh? What rules?

I wonder if there would be any interest in the RC2014 community for a 64K RAM/ROM (EEPROM) card design with simpler, more flexible, memory mapping capability to support both Z80 and 65C02 CPU cards? Basically you map ROM and all remaining space goes to RAM, qualified of course by the MREQ signal. Configure ROM in low memory starting at $0000 for Z80 or in high memory ending at $FFFF for 65C02. It's especially easy to setup Grant Searle's original 8K ROM ($0000..$1FFF) and 56K RAM ($2000..$FFFF) memory map.

I've been working on routing a layout (below).

Cheerful regards, Mike, K8LH

Why not shadow the ROM and switch it out after boot.
You can even have a two speed clock to deal with slower
EEPROM speeds.
That way you can even update the EEPROM in system.
You have the advantage of the maximum RAM space when needed
or even testing out changes to the monitor or such.
I did this on a computer I modified to do the shadowing ( single speed
clock ). It wasn't much more than a tiny amount of glue logic.
It was quite handy for testing and debugging.
Dwight