Well, I've been toying around with looking into this whole programmable-logic thing, and I think I've come up with a suitable design. The new memory-mapper logic is intended to give a ROM window of up to 16KB at the top of memory, selectable between eight sizes (size 0 being no ROM.) The ROM is further divided into two 8KB banks which can be selected out of a standard 32KB ROM (though at any size below 16KB only the top bank will be visible.) And writing to the ROM window will write to the RAM underneath.
I worked up what I
think is a valid representation of this in CUPL and I think I've got the logic sorted out. However, I'm having a heck of a time compiling and testing it in WinCupl and WinSim, which is possibly due to human error on my part, but I more think might be due to its being 1998-vintage software running on my Windows 8 work machine. I'll have to try it on my XP laptop at home tomorrow. In the meantime, if somebody wants to proofread my clumsy first attempt at this stuff, here's the source for the PLD and SI files:
MEMORY MAPPER.PLDCode:
Name Memory mapper ;
PartNo 00 ;
Date 7/7/2017 ;
Revision 01 ;
Designer commodorejohn ;
Company Northland Computers ;
Assembly None ;
Location ;
Device g22v10 ;
/* *************** INPUT PINS *********************/
PIN [1..8] = [A8..A15] ; /* High-order CPU address lines */
PIN 9 = !MREQ ; /* Memory request enable */
PIN 10 = !WR ; /* Write enable */
PIN 11 = SZ0 ; /* ROM window size */
/* PIN 12 = Gnd */
PIN [13..14] = [SZ1..SZ2] ; /* ROM window size */
PIN [15..16] = [BNKA0..BNKA1] ; /* ROM bank A ($C000-DFFF) page select */
PIN [17..18] = [BNKB0..BNKB1] ; /* ROM bank B ($E000-FFFF) page select */
/* *************** OUTPUT PINS *********************/
PIN [19..20] = [ROMA13..ROMA14] ; /* High-order ROM address lines */
PIN 21 = !RAMSELA ; /* RAM A select */
PIN 22 = !RAMSELB ; /* RAM B select */
PIN 23 = !ROMSEL ; /* ROM select */
/* PIN 24 = Vcc */
/* Fields */
FIELD ROMSIZE = [SZ0..SZ2] ; /* ROM window size */
FIELD ADDRMSK = [AM8..AM13] ; /* Bits to ignore in checking for top-of-memory */
/* Truth table for address mask */
TABLE ROMSIZE => ADDRMSK {
0=>00; 1=>00; 2=>01; 3=>03;
4=>07; 5=>0F; 6=>1F; 7=>3F;
}
/* Equations */
ROMENA = SZ0 # SZ1 # SZ2 ; /* ROM enable only if window size is not 0 */
VARADR = (A13 # AM13) & (A12 # AM12) & (A11 # AM11) & (A10 # AM10) & (A9 # AM9) & (A8 # AM8) ; /* Address lines for compare, optionally forced to 1 */
TOPMEM = ROMENA & A15 & A14 & VARADR ; /* Top-of-memory area (inside ROM window) */
RAMSELA = !A15 & MREQ ; /* RAM A select if A15 = 0 and MREQ = true */
RAMSELB = A15 & MREQ & !TOPMEM ; /* RAM B select if A15 = 1, MREQ = true, top-of-memory = false */
ROMSEL = TOPMEM & MREQ & !WR ; /* ROM select if top-of-memory = true, MREQ = true, and WR = false */
ROMA13 = (BNKA0 & !A14) # (BNKB0 & A14) ; /* Page select for ROM A13 */
ROMA14 = (BNKA1 & !A14) # (BNKB1 & A14) ; /* Page select for ROM A14 */
MEMORY MAPPER.SICode:
Name Memory mapper;
PartNo 00;
Date 7/7/2017;
Revision 01;
Designer commodorejohn;
Company Northland Computers;
Assembly None;
Location ;
Device g22v10;
ORDER: A8, A9, A10, A11, A12, A13, A14, A15, BNKA0, BNKA1, BNKB0, BNKB1, !MREQ, !RAMSELA, !RAMSELB, ROMA13, ROMA14, !ROMSEL, SZ0, SZ1, SZ2, !WR, ADDRMSK, ROMSIZE;
VECTORS:
/* MREQ = F for RAMA, RAMB & ROM at all sizes */
/* Test for all select lines high */
/* MREQ = F, A15 = 0 */
00000000XXXX1HHNNHXXX1NN
/* MREQ = F, A8-15 = BF, SZ0-2 = 7 */
11111101XXXX1HHNNH1111NN
/* MREQ = F, A8-15 = DF, SZ0-2 = 6 */
11111011XXXX1HHNNH0111NN
/* MREQ = F, A8-15 = EF, SZ0-2 = 5 */
11110111XXXX1HHNNH1011NN
/* MREQ = F, A8-15 = F7, SZ0-2 = 4 */
11101111XXXX1HHNNH0011NN
/* MREQ = F, A8-15 = FB, SZ0-2 = 3 */
11011111XXXX1HHNNH1101NN
/* MREQ = F, A8-15 = FD, SZ0-2 = 2 */
10111111XXXX1HHNNH0101NN
/* MREQ = F, A8-15 = FE, SZ0-2 = 1 */
01111111XXXX1HHNNH1001NN
/* MREQ = F, A8-15 = FF, SZ0-2 = 0 */
11111111XXXX1HHNNH0001NN
/* MREQ = F, A8-15 = C0, SZ0-2 = 7 */
00000011XXXX1HHNNH1111NN
/* MREQ = F, A8-15 = E0, SZ0-2 = 6 */
00000111XXXX1HHNNH0111NN
/* MREQ = F, A8-15 = F0, SZ0-2 = 5 */
00001111XXXX1HHNNH1011NN
/* MREQ = F, A8-15 = F8, SZ0-2 = 4 */
00011111XXXX1HHNNH0011NN
/* MREQ = F, A8-15 = FC, SZ0-2 = 3 */
00111111XXXX1HHNNH1101NN
/* MREQ = F, A8-15 = FE, SZ0-2 = 2 */
01111111XXXX1HHNNH0101NN
/* MREQ = F, A8-15 = FF, SZ0-2 = 1 */
11111111XXXX1HHNNH1001NN
/* MREQ = T for RAMA, RAMB & ROM at all sizes */
/* Test for RAMA low */
/* MREQ = F, A15 = 0 */
00000000XXXX0LHNNHXXX1NN
/* Test for RAMB low */
/* MREQ = T, A8-15 = BF, SZ0-2 = 7 */
11111101XXXX0HLNNH1111NN
/* MREQ = T, A8-15 = DF, SZ0-2 = 6 */
11111011XXXX0HLNNH0111NN
/* MREQ = T, A8-15 = EF, SZ0-2 = 5 */
11110111XXXX0HLNNH1011NN
/* MREQ = T, A8-15 = F7, SZ0-2 = 4 */
11101111XXXX0HLNNH0011NN
/* MREQ = T, A8-15 = FB, SZ0-2 = 3 */
11011111XXXX0HLNNH1101NN
/* MREQ = T, A8-15 = FD, SZ0-2 = 2 */
10111111XXXX0HLNNH0101NN
/* MREQ = T, A8-15 = FE, SZ0-2 = 1 */
01111111XXXX0HLNNH1001NN
/* MREQ = T, A8-15 = FF, SZ0-2 = 0 */
11111111XXXX0HLNNH0001NN
/* Test for ROM low */
/* MREQ = T, A8-15 = C0, SZ0-2 = 7 */
00000011XXXX0HHNNL1111NN
/* MREQ = T, A8-15 = E0, SZ0-2 = 6 */
00000111XXXX0HHNNL0111NN
/* MREQ = T, A8-15 = F0, SZ0-2 = 5 */
00001111XXXX0HHNNL1011NN
/* MREQ = T, A8-15 = F8, SZ0-2 = 4 */
00011111XXXX0HHNNL0011NN
/* MREQ = T, A8-15 = FC, SZ0-2 = 3 */
00111111XXXX0HHNNL1101NN
/* MREQ = T, A8-15 = FE, SZ0-2 = 2 */
01111111XXXX0HHNNL0101NN
/* MREQ = T, A8-15 = FF, SZ0-2 = 1 */
11111111XXXX0HHNNL1001NN
/* WR = T for ROM at all sizes */
/* Test for RAMB low */
/* MREQ = T, A8-15 = C0, SZ0-2 = 7 */
00000011XXXX0HLNNH1110NN
/* MREQ = T, A8-15 = E0, SZ0-2 = 6 */
00000111XXXX0HLNNH0110NN
/* MREQ = T, A8-15 = F0, SZ0-2 = 5 */
00001111XXXX0HLNNH1010NN
/* MREQ = T, A8-15 = F8, SZ0-2 = 4 */
00011111XXXX0HLNNH0010NN
/* MREQ = T, A8-15 = FC, SZ0-2 = 3 */
00111111XXXX0HLNNH1100NN
/* MREQ = T, A8-15 = FE, SZ0-2 = 2 */
01111111XXXX0HLNNH0100NN
/* MREQ = T, A8-15 = FF, SZ0-2 = 1 */
11111111XXXX0HLNNH1000NN
/* Todo: ROMA13-14 for all values of BNKA & BNKB in both banks */
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