On the board update time, it looks like a bootstrapping problem. I am tring to avoid using the CPLD chip for gating logic and do it simply. the dictate is to throw the string "WDC" in your eprom at $8000 and begin your program at $8004. It doesnt want to work that way because of some bootstrap madness on my part.

I am using the chip select outputs CS7B for the eprom and CS3B for the external RAM. It wont do it there.

I am going to try and emulate the memory map outside via ttl logic and see how it all goes.

the first logic equation from the CPLD is to use /A15 for the chip select for the eprom. going for that first. external RAM is going to be a tad harder, and I am stikll curious as to allowing it to use the upper 4K mask library rom in there.

will keep the adventures of the Swedish 6502 chef maniac going....

_________________
"My biggest dream in life? Building black plywood Habitrails"

And the inverted A15 WORKS. It also means that it wont access the internal mask rom for now. The typical reset vector stays at the top.

the program below is the first running program here, a simple typical blinkenlights program. One of the ports I have a 74ls374 running LEDs. It uses the output port to send out 8 bits and uses the port strobe to clock the 374. I put in port 6 for variosu lines for the output boards for later on. this is a dumb test code. I brought down the clock crystal to 4 MHz and I threw in a 62256 from my pinball board.

the correct decode logic for the RAM and things is a tad big to implement in TTL logic, but it CAN be done. WDC is partnered with Lattice and will have an FPGA for thiese tasks, much like the CPLD on their designer board.

I am trying for a push for a hobby package with the 65C134, the Lattice chip and instructions from what I am going wild with out here

anyhoo, here is the first dumb program. Good programming code? Naw, this is giggle code. you look at the code and giggle..

Bork! Bork! Bork!

; 65C134 QC Test Fixture Microcontroller Code
; Antonio Gonzalez jr. 2006
;
; SYSTEM
;
; CPU: 65C134 8 MHz
; ROM: 27C256 32K Eprom
; RAM: 6264 8K RAM
; I/O: 8 parallel ports, RS232 port
;
;
; * * * System memory Map & Hardware Equates * * *
;
; $0000-$1fff 8K RAM (external)
; $8000-$ffff 32K Eprom
; $2000 CS3B for the LED
; $0000-$002f internal registers
; $0040-$00ff internal RAM
;

; Ports are defined as follows:
; P4 = Port Enables. they are defined as follows:
; P40 = port 0
; P41 = port 1 etc.
; active low.
;
; P5 = Port data Bus. P50 = d0, P57 = d7
;
; P6 = port control lines/RS232 as follows:
; P60 = RS232 Rxd
; P61 = RS232 Txd
; P62 = PortA0
; P63 = PortA1
; P64 = PortA2
; P65 = PortR//W
; P66 = PortClock
; P67 = Port/Irq

; Chip Select Register.
PCS =$0007

; I wont need to define the BCR for now since the power up init sets it where needed.
BCR =$001b


; think of these ports like the 65C22 and you should be ok
Port4Data =$001c
Port5Data =$001d
Port6Data =$0020
Port4PortDir =$001e
Port5DataDir =$001f
Port6DataDir =$0021



;
; * * * Variable Equates * * *
; dont forget that variable space begins at 0040 since lower are registers. will figure out where to
; stick the stack later on...

CountMSB =$0040
CountLSB =$0041






; * * * The ROM beings HERE * * *

.ORG $8000

; Program identifier table
; this is out until I can figure out how to do the bootstrapping correctly for this entire
; shebang...

*= $8000
; .byte "WDC" ;this is used to identify the eprom to the 65C134

; *=$8004 ; go ahead and start your program here.



; Write zeroes into p4, p5, p6
LDA #$00
STA Port4Data
STA Port5Data
STA Port6Data

; turn all P4 p5 and p6 to outputs
LDA #$ff
STA Port4PortDir
STA Port5DataDir
STA Port6DataDir
STA CountMSB
STA CountLSB


Loop
JSR BlinkenlightON
JSR BigDelay
JSR BlinkenlightOFF
JSR BigDelay
JMP Loop


BlinkenlightON
LDA #$ff
STA Port5Data
LDA #$80 ; strobe the enable clock
STA Port4Data
JSR TinyDelay
LDA #$00
STA Port4Data
JSR TinyDelay
LDA #$80 ; strobe the enable clock
STA Port4Data
JSR TinyDelay
LDA #$00
STA Port4Data
RTS

BlinkenlightOFF
LDA #$00
STA Port5Data
LDA #$80 ; strobe the enable clock
STA Port4Data
JSR TinyDelay
LDA #$00
STA Port4Data
JSR TinyDelay
LDA #$80 ; strobe the enable clock
STA Port4Data
JSR TinyDelay
LDA #$00
STA Port4Data
RTS



; ok, so it ain't elegant, but it does the job, cheap and easy, that's me...

TinyDelay
LDX #$ff
TinyDelay1
DEX
BNE TinyDelay1
RTS

BigDelay
LDX CountMSB
LDY CountLSB
BigDelay1
DEY
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
BNE BigDelay1
LDY CountLSB
DEX
BNE BigDelay1
RTS


; reset vector
; Just hang it over to 8000 for now, mate

*= $fffc
.BYTE $80,00
.BYTE $80,00

_________________
"My biggest dream in life? Building black plywood Habitrails"

Ok, new updates time.

1. Code rewritten, make it a tad easier. The one above works, but it gets stupid in style.

2. The blinking red LEd on the chip select was a lousy idea. On my older one, I threw it onto A7 and merely crossed page boundaries to fire off the LED. It worked. A chip select WILL fire off correctly, but you can detect no light difference, so that is useless. Instead, I modified the boards, the two unused NAND gates became an RS flip flop and those drove the LED. Two chip select lines were used to set and reset the flip flop. It workes GREAT.

Am modifying thee board, the updated schematic is in my usual place of www.nightmarepark.com/6502.php



today's other fun project is seeing on getting the external RAM to work without major bufu logic. If I cant, I will stick with the cpld array for ram usage and rely on the 192 bytes within and merely write penurious code...

_________________
"My biggest dream in life? Building black plywood Habitrails"

Ok, had fun fighting with the ram code. Here is the fun festivities.

1. The indirect indexed I used for my pinball self test of RAM was crashing and burning on th 134. Still havent figured it out. I ended up cheating and simply using an absolute Y indexed bugger. It only tests 255 bytes, but that is enough to hang out with.

2. The 8K ram CANNOt be put to the lower memory without some CPLD fun and games. there is some tricky logic inside that logic gate required, and I didnt want to add a whole slew of chips to do it.

I ended up putting the 8K ram a tad higher. WDC recommended putting at CS6B which places it quite high. The problem I found was the same as using CS3B: it moves the memory stack offchip and tries to stick it in an outboard ram area that doesnt exist. Crash and burn again.

I put the 8K ram at CS5B, 4000-5fff. Ram self test worked this time, so the logic is correct. for proof, taking the ram out of the socket caned the ram self test to fail.

Friday's festivities will be to activate the library rom inside. If I cant get it done, I will merely copy the relevant code out to the 32K rom and use from there

<<<itinerant brat...

_________________
"My biggest dream in life? Building black plywood Habitrails"

You should write an article for the website when you're done, detailing your experiences with the chip. From what it sounds like you're going through, I'm very glad that I didn't follow through with WDC's recommendation that I use a 65C265 for redesigning the Kestrel project. I can honestly say that I've never had any problems using (),y mode with the 65C816 directly.

Good idea. Perhaps all this can be rewritten into a diary of sorts.

They are talking at WDC about my findings so far, they have the code and everything


2 days ago, got the RAM running though. I used a simple indexed to do a 255 byte ram rtest which works, the

lda ($0000),y in a loop.

I found out that if I tried using CS3B or CS6B, it would pull the onchip ram STACK offchip where ididnt have RAM hooked up.

I had hooked up 8K of ram at a different asdddress of CS5B, locations 4000-5fff and the test for it worked perfectly, claiming bad RAM when the ram is removed and t4esting good when it is.



the real caveat towards using the 134 and 265, there are siome slightly ugly glu logic setups to make the special functions work great such as the outboard ram and mask ROM. do not forget I have trying to interface as simple as possible WITHOUT using the glu logic cpld.

For a later revision or design, I would DEFINITELY use a glu logic. WDC is working with Lattice for an improved logic setup.

I am trying to talk them into releasing the two key components of the cpu and glu logic chip together as a set for us experimenters.

It is a chip worth definitely for us experimenters. am glad to ebe cranking away at it. Am having a blast in the learning. Hope it can help for anyone else who wants to jump into it as well.


for today's work, I am trying to get the internal Mask rom to work without crashing the works as it was doing 2 days ago. if that doesnt work, I will merely copy the mask rom library over to my eprom and use the routines from there.

Kc5: I think tis still worth it to use. dont close it out for the future.

_________________
"My biggest dream in life? Building black plywood Habitrails"

And got the internal rom to be readable. Once again, I cannot use the WDC entry code as is recommended, I had to run the flag manually for a

lda #$80
TRB BCR

The trick is resetting the BCR7 to 0 using the TRB command. doing a simple load and store crashes things.

to do a verify, I put a small readout loop to clock out the drom to the parallel port, once a second. seems to do the trick.

Latest working code in my usual funspot.

today's festivities are to use the serial port and output a string to the host computer. Once that is sucessful, then I go the other way...

_________________
"My biggest dream in life? Building black plywood Habitrails"

More adventures days...


1. 80 nS RAMs will NOT work at 8 MHz clocking. I had the outboard RAM working beautifuly and then today, zip, zilch, nada. running too fast. So back to the 4 MHz fast clock.

2. The RS232 routines DO need the second crystal, so the board is now modified for a 32.768 kHz crystal. Cant find an oscillator of that speed. Sigh.

3. had some VERY wierd fun, had a Hello World program designed to output the phrase from the RS232 port. As an extra test, I also had the datat coming out of the output slots. Guess what? when I invoked ACI_Init from the mask ROM, the output slots would die! VERY freaky fun.

The Answer? My design. when ACI_Init is invoked, it sets up P60 and P61 for RS232. It ALSO sets up P40 as an input and P44-P47 for the SIB networking bus. I am using THOSE as outputs selectors, port enables.

so tomorrow, I am copying the ACI_init routines into my program rom but editing out the P4 extraneous festivities.

also, one gotcha to stupid code technoqies on my part was in not preserving A X and Y when I would do my delay routines. using Y adressed fun such as the RAM tests, it would simply cause hilarity to ensue..


and the 65C134 hacking express merilly rolls along...

;
; 65C134 QC Test Fixture Main Program
; Antonio Gonzalez jr. 2006
;
; SYSTEM
;
; CPU: 65C134 8 MHz
; ROM: 27C256 32K Eprom
; RAM: 6264 8K RAM
; I/O: 8 parallel ports, RS232 port
;
;
; * * * System memory Map & Hardware Equates * * *
;
; $0000-$002f internal registers
; $0040-$00ff internal RAM
; $4000-$5fff 8K RAM (external)
; $8000-$ffff 32K Eprom
; $2000 CS3B for the LED
;
; Ports are defined as follows:
; P4 = Port Enables. they are defined as follows:
; P40 = /Port7En
; P41 = /Port6En down to /Port0En
; active low.
;
; P5 = Port data Bus. P50 = d0, P57 = d7
;
; P6 = port control lines/RS232 as follows:
; P60 = RS232 Rxd
; P61 = RS232 Txd
; P62 = PortA0
; P63 = PortA1
; P64 = PortA2
; P65 = PortR//W
; P66 = PortClock
; P67 = Port/Irq


PD3 =$0003 ; CS Port Register
PCS3 =$0007 ; CS Bit Enable Register
BCR =$001B ; BCR Register

; think of these ports like the 65C22 and you should be ok
Port4Data =$001c
Port5Data =$001d
Port6Data =$0020
Port4PortDir =$001e
Port5DataDir =$001f
Port6DataDir =$0021
RedLightOFF =$0120
RedLightON =$0100


; Mask ROM Vector Equates
; RS232 port calls

AciaInit =$f003 ; Init serial ACIA
ReadChar =$f006 ; Read a character
ChkContC =$f009 ; Check for control C pressed
CrLf =$f012 ; Prince a carriage return & linefeed
PrintSpace =$f015 ; Print a space
GetChar =$f00c ; Get a character with wait
OutChar =$f00f ; write a character
ReadHexAddr =$f021 ; Read address in ascii hex
ReadHexByte =$f024 ; Read byte in ascii hex
WriteHexAddr =$f027 ; Write address in ascii hex
WriteHexByte =$f02a ; Write byte in ascii hex
MS19Out =$f042 ; Output S19 records
MS28In =$f045 ; Input S records

; Data manipulation fuctions

AscToBin =$f018 ; Ascii to binary conversion
BinToAsc =$f01b ; binary to ascii conversion
BinToDec =$f03f ; binary to decimal conversion
CalcChecksum =$f048 ; Calculate checksum
AscHexToBin =$f03c ; Ascii Hex to binary
CheckForAscLtr =$f030 ; Check for ascii
CheckForAscNum =$f02d ; Check for ascii decimal number
MoveDataBlock =$f036 ; Move data block
UpperCase =$4033 ; Convert character to uppercase ascii















;
; * * * Variable Equates * * *
; dont forget that variable space begins at 0040 since lower are registers. will figure out where to
; stick the stack later on...
; use the external RAM at 4 MHz MAXMIMUM, and no higher, thanks!

DelayCountLSB =$4000
DelayCountMSB =$4001
CountLSB =$4002
CountMSB =$4003
CountY =$4004
SlotEnableNum =$4005
DataFromSlot =$4006
DataToSlot =$4007
Temp1 =$4008
Temp2 =$4009



; * * * The ROM beings HERE * * *

.ORG $8000

; Program identifier table
; this is out until I can figure out how to do the bootstrapping correctly for this entire
; shebang...

*= $8000
; .byte "WDC" ;this is used to identify the eprom to the 65C134
; *=$8004 ; go ahead and start your program here.
; Please note that the WDC will NOT work with my code. will have to activate the library...manually...

; Setup Thy Chip Environment
Setup
LDA #$26
TSB PCS3 ; Enables CS5B, CS2B and CS1B. Use the TSB to not munge up the flags.
LDA #$80 ;turn on the mask ROM, please.
TRB BCR

; Setup thy Variables
LDA #$00
STA Port4Data ; Ports like the 65C22
STA Port5Data
STA Port6Data
STA RedLightOFF ; Reset the flip flop
STA RedLightON
STA RedLightOFF
LDA #$ff
STA Port4PortDir ; Write only outputs for now, the Port/Irq will become an input
STA Port5DataDir
STA Port6DataDir
STA DelayCountMSB
STA DelayCountLSB
LDA #$80
TSB SlotEnableNum; only slot 0 for now.



LDA #$07 ; 2400 baud
LDX #$08 ; 8 bits
LDY #$00 ; no parity
; JSR AciaInit
CMP #$ff
BEQ BadSerialInit ; hope it inited ok...
JMP Setup2

BadSerialInit
JSR TurnRedLightOFF
JSR BigDelay
JSR TurnRedLightON
JSR BigDelay
JSR TurnRedLightOFF
JSR BigDelay
JSR TurnRedLightON
JSR BigDelay
JSR TurnRedLightOFF
JSR BigDelay
JSR BigDelay
JSR BigDelay
JSR BigDelay
JSR BigDelay
JMP BadSerialInit

Setup2
LDY #$00

Loop
LDA SerialString,y
JSR PushToSerial
INY
CPY #$0c
BEQ Setup2
JMP Loop


PushToSerial
; JSR OutChar
LDA SerialString,y
STA DataToSlot
JSR WriteToSlot
JSR TurnRedLightON
JSR BigDelay
JSR TurnRedLightOFF
JSR BigDelay
RTS






; Library Routines

TurnRedLightOFF
LDA #$00
STA RedLightOFF
RTS

TurnRedLightON
LDA #$00
STA RedLightON
RTS

WriteToSlot
LDA DataToSlot
EOR #$ff
STA Port5Data
LDA SlotEnableNum
STA Port4Data
JSR TinyDelay
LDA #$00
STA Port4Data
JSR TinyDelay
LDA SlotEnableNum
STA Port4Data
JSR TinyDelay
LDA #$00
STA Port4Data
JSR TinyDelay
RTS

ReadFromSlot
LDA SlotEnableNum
STA Port4Data
JSR TinyDelay
LDA #$00
STA Port4Data
JSR TinyDelay
LDA Port5Data
STA DataFromSlot
LDA SlotEnableNum
STA Port4Data
JSR TinyDelay
LDA #$00
STA Port4Data
JSR TinyDelay

RTS






TinyDelay
PHX
LDX #$ff
TinyDelay1
DEX
BNE TinyDelay1

PLX
RTS

BigDelay
PHX ; Save it, willya? Thanks
PHY
PHA
LDX DelayCountMSB
LDY DelayCountLSB
BigDelay1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DEY
BNE BigDelay1
LDY DelayCountLSB
DEX
BNE BigDelay1

PLX ; Bring 'em back alive!
PLY
PLA
RTS




*=$e000
SerialString:
.BYTE "H"
.BYTE "e"
.BYTE "l"
.BYTE "l"
.BYTE "o"
.BYTE " "
.BYTE "W"
.BYTE "o"
.BYTE "r"
.BYTE "l"
.BYTE "d"



; reset vector
; Just hang it over to 8000 for now, mate

*= $fffc
.BYTE $80,00
.BYTE $80,00







Anyhoo, the working Hello World code so far is as follows...

_________________
"My biggest dream in life? Building black plywood Habitrails"

Ok, got the ACI_INIT bug fixed up. I m erely copied the old code and did a bit reset where the old would set, and vice versa (vice versa = dirty limericks).

Already posted up the updated code in my webspace asalways.

Only bummer for the day, found a fun bug or incompatibility with the Kowalski assembler. It does NOt like using opcode reserves as variables. The original Romnlist of the 65C134 uses SEC as a variable for the time of day clock seconds. I duplicated all the variables used in the 65C134 as reference since I still cannot do the proper method of rom working. this way,m the rom sub programs have their variables to reference to. I will have to find a workaround for SEC then.

At this point, putting the OUTCH (character out to RS232) is freezing up, so that is now the bug for the day to fix up.


Anyhoo, the fix code FYI to disable the SIB bus festivities is as follows:

LDA #$80 ; this will reset P44-P47 as the ACI_Init changes those for the serial bus
TSB PDD4 ; and I am USING those bus as bus enables for the slots, thanks!
LDA #$08 ; Now lets fix up the IER from the trepidations...
TRB IER1
LDA #$02 ; and fix up the BCR
TRB BCR

NOTE: you CANNOT use STA commands on status registers in the 65C134 It hates life when you do. Use the TSB and TRB. The ports outputting seem to be ok with the STA command, though. Go figure.



As a different aside, if any of you are round Burbank this weekend, I will be out there at the Horrorween booth, signing autographs and selling my CD and pressing the flesh. gotta have some fun in life, ya know...(and once this movie gig is over, THEN I can FINALLY get back to the pinball project!)

_________________
"My biggest dream in life? Building black plywood Habitrails"

And the general adventures continue.

Ok, port software running, check.
my software running, check

Time for the RS232 fun. Got the inits programmed in, they hook in right, check.

Hit the CLI, enable interrupts.

BOOM


dead as a doornail.


Roy at WDC (ok, I think I owe you an entire CASE of beer by now for all the help you've helped me with) sent me a small init to get the RS232 going.

Still dead at the same place. Code runs GREAT until the interrupts get enabled.


Pullups on the interrupt line?

nope.

The answer?

RDY line seems to want interrupt acknowledges.

time top make a tiny hardware patch to get the acknowledge going.


I am wondering if I should just use a CPLD with equations to get things going here.


fun gotcha. reast of things were running great till the interrupt gets going.

Sigh.

Anyhoo, Indiana Tony here blazes the way through the jungle, enjoying himself every step of the way.


Oh, it could have had a stupid easy sidestep. was considering using a 2051 to my port to send out RS232 translations, right?

Once I started THAT bit of cheese, then I realized why the heck I wanted to stay the hell AWAY from the 2051.

String is 32 bytes, OUT OF MEMORY?

Keep me in the 65134 jungle.

I am having more fun.

and bringing back kewl movies as well

_________________
"My biggest dream in life? Building black plywood Habitrails"

Ok, yesterday was bananas. Made one final big assertion after all thsi time.

I can't use interrupts. Period. Lockup city.

Interrupts WORK on the WDC board.

This aint that board.

I found a wierd trick to get the RS232 coming out. Turn ON the interrupts to set things up, then turn them OFF again just as fast.

CLI
NOP
SEI

insanity code right there. But it works.

I went absolutely bonkers, I figured out doing an event loop to read the UART data read register and debounce it, right?

Found out WHY the program didnt work THERE.

when interrupts are out, the register holds the last value and wont change until a new different value is popped in from the RS232 recieve.

armed with the insane knowledge, I then passed the psychiatric evaluation and concocted a shift register routine of bytes.

When a byte comes in, it stays. when it turns DIFFERENT, it shifts through 2 values and sets a flag that it is done and ready for the cooker.

so now I was able to use an event loop, sending things out of the RS232 ANd reading it. ionly 2 caveats.

1. No type buffer.
2. I cannot use the same character 2 times in a row. I can use any other in between, so the idea to program the bugger is to use / to have the typing /l/o/o/k/ /l/i/k/e/ /t/h/i/s/

but it works.

By Golly, it works. RS232 send/recieve with no interrupts on the 134.

The code is below
; Main loop has to process inputs and outputs like the pinball loop.
; thankfully, the inputs are single character for modes.


; all the setups, no need to reiterate

MainLoop
JSR GetChar
JMP InputParser ; This way, I dont mess up the stack
MainLoop1
JSR ProgramLogic
JSR OutChar
JMP MainLoop

; Input routine.
; the variables and actions they do.
; ARTD input raw
; TempARTD compare with ARTD to see if different
; RS232Input holds the output product
; RS232InputReady shows output is ready, outside program clears it
GetChar
LDA RS232InputReady
CMP #$01
BEQ GetChar1
STZ RS232InputReady ; Clears the flag, ready for more action
GetChar1
LDA ARTD
CMP TempARTD
BEQ GetCharEnd ; Char still the same
STA TempARTD
STA RS232Input
LDA #$01
STA RS232InputReady
GetCharEnd
RTS

OutChar
CMP #$00 ; No repeating $00's, thank you!
BEQ OutCharEnd
STA ARTD ; out it goes!
JSR SendDelay
OutCharEnd
RTS


simple to understand, yet inventors of 6502 now think I have gone off the deep end

Maybe I have, but it flashes pretty little lights on command at work.

Makes for GREAT demonstrations when the bosses want to see what is going on here....

_________________
"My biggest dream in life? Building black plywood Habitrails"

kc5tja



Joined: 04 Jan 2003
Posts: 509
Location: San Diego, CA

PostPosted: Thu May 11, 2006 6:52 am Post subject: Reply with quote
You should write an article for the website when you're done, detailing your experiences with the chip. From what it sounds like you're going through, I'm very glad that I didn't follow through with WDC's recommendation that I use a 65C265 for redesigning the Kestrel project. I can honestly say that I've never had any problems using (),y mode with the 65C816 directly.


I found my problem was in the LSB, MSB order in defining the variables. Indexing worked fine after I took care of my stupid error there.


this chip really is worth the whirl. I am on a fast ride but enjoying the heck out of it. Had to work hard to get to where its at today, but it IS a fun journey. Experimenter-wise, it blows away any PIC or microcontroller I've seen. I make mistakes left and right, I write first grader code and this chip is patiently teaching me where to go.

will have a suprise soon concerning this project to announce....

_________________
"My biggest dream in life? Building black plywood Habitrails"

Some suprises still in store soon, but the general update on things.

1. I got laid off from work today. The test fixture MAY continue, but as an outside contract. This is still negotiable and my most important thing is finding another job. If anyone has an Orange County or Riverside County lead, please let me know, I will owe some good dinner on that one.
2. 3 months ago was when I had started out the revision 2 of the motherboard for the CPU. (it got frozen as work suddenly decided that the lab was better suited to menial production line inspections). I had some great suggestions thrown to me, and this revision 2 will be offered both for sale and as a download to build your own as a development system to use the 65C134. Some new features included are:

> external memory and ports ribbon connectors
> TIDE compatibility
> onboard voltage regulator
> CPLD for assignable logic functions
> RS232 port

The reason I am setting out to release in this manner is that none of us have been into this chip, and it is a seriously FUN chip. It has a lower chip count and more bang for the buck using the 134 and a CPLD for gating logic rather than a 65C02 and 2 65C22 ports.

I also have on the drawing board a helluva nice graphics system to be compatible with it This was going to go for the test fixture, but it is now for general experimental release. It is based on a Japanese simple 3 chip design, but is redone to my own spec.

The redesign was because I simply gave up trying to find the mystery of why no interrupt action I could ever discover. The wierd code hack to work around the interrupts worked quite well, but it proved to be a dead end. I was able to prove that the 65C134 CAN be used with the simple 02 qualification of the R/W line, identical to the 65C02. By means of using the CPLD, more improved logic functions can be used.

So once again, this is a watch this space...

_________________
"My biggest dream in life? Building black plywood Habitrails"

OUCH. That is a bummer! I wish I could help there.

I've been SUPER busy of late -- my professional job is just draining every ounce of initiative from me. What little time I have to spend on projects is done currently implementing my OpenAX.25 software, as I am now a member of the AX.25 layer 2 protocol special interest group (the folks who maintain the protocol and evolve it).

Besides, once OpenAX.25 is done, you can bet it might make an appearance somewhere in the Kestrel.



It seems to me like you've had a number of major problems with the chip, though -- problems that would not have been encountered using the more discrete approach. Frankly, your issues with the chip gives me serious reservations about using it.

The chip issues were probably more with me trying to go discrete in the first place. There is a mild amount of logic gate work to get a full implementation, on the order of 10 TTLs or so. I decided to go clean slate with the CPLD instead of patching up my original design. I think this will solve the issues I've had with the interrupts. With the total redesign, I am also learning from ym mistakes and making a more robust and solid board, plus with more functionality than before. My old board I had the 8 slots on the same board. For the new version, it will have a 40 pin ribbon connector and the 8 slots will be an outboard board. A secoind 40 pin ribbon connector will allow external memory access, and some extra lines from the CPLD can be reprogrammed to any function desired.

Once you get past prototyping woes from my dimwitted way of going about it the first time, it is a joy to use and I do plan to use it in future applications. I want to keep the pinball project to use straight parts, but I am SERIOUSLY tempted to redesign the hardware to use the 134 and CPLD. The downshot there is that I was going for straight TTL to make it easy to work with in 20 years. Actually, the CPLD is common enough so I think it may be worth looking into for the pinball circuit. It would reduce my cost something fierce there, instead of 15-30 TTLs, just simply a 4 or 5 chip circuit. So I am thinking of looking into that. If it looks good, I will do the hardware redesign to use it and redo the code as needed.


Resumes EVERYWHERE last night, I went to town

_________________
"My biggest dream in life? Building black plywood Habitrails"