LIV2 wrote:
So besides RD & WR, Active high Reset, IACKN what other differences are there to consider?
I know that usually in a 68xxx system bus operations are synchronized with DTACK, however the datasheet states
Quote:
Systems not strictly requiring DACKN may use the 68xxx mode with the bus timing of the 80xxx mode greatly decreasing the bus cycle time.
And I'm pretty sure IACKN can just be tied high and ignored right?
IACKN can be pulled up to Vcc and ignored, as the 28L92 timing doesn't have any special dependency on it.
As for as whether to use Intel or Motorola bus mode, my experience is that Intel mode is the way to go with the 65C816, as the 28L92's read and write operations are separately controlled. With the '816, I/O hardware must stay off the data bus (or be isolated with a bus transceiver) during Ø2 low in order to avoid contention when the '816 emits the bank bits. This is readily accomplished by gating the
/RD and
/WD signals with Ø2 high. Also, the 28L92 can be confused by the change of the data bus during a write cycle that occurs when Ø2 goes high, especially when accessing the command registers. Hence not asserting the
WRN input on the 28L92 until Ø2 goes high is essential. In Motorola mode you don't have that control.
Either mode should be usable with a 65C02 machine, since the data bus behavior is less convoluted. Motorola mode will likely entail a little less glue logic.