Hi (new-ish here)

[piemmm]

Hi!

I've spent a couple of days designing my first board (after messing about with a bit of breadboard so I almost know what I'm doing) using some of the info on here and around the net as well

Haven't done this before so it seems like an interesting project to do and learn stuff whilst I'm at it

It probably won't work (see attached pic) when I get it back from the fab, but that's all part of the learning expierience!

[barrym95838]

It's beautiful, Ian! And it's a very ambitious first attempt. You have my sincere congratulations if it works, and my condolences if it turns into an expensive paper weight.

Mike B.

[Arlet]

Do you have a schematic you can post as well ?

[BigEd]

Welcome! I'd be interested to know more about the memory map and system architecture. Looks like you have big ROMs and a big RAM for each ROM - some kind of multi-tasking idea?

[Mike Naberezny]

barrym95838 wrote:

It's beautiful, Ian! And it's a very ambitious first attempt.

Wow, I agree, that's quite a board for a first try. Good luck with the bring up!

What do you have planned for all the ROM space?

[piemmm]

Hi!

A yes on the schematic (once I've found out if it's working or not - I want to find out myself if I messed something up badly )

The ROMS are for whatever ideas I have - at some point,... /if/ this all works out , I'll probably opensource all the bits.. a fairly big if at the moment as I have a lot of stuff to write once the boards are made! The design is a bit of fun with no paticular goal in mind and I've been a big fan of jumping into something new with both feet

The memory map has trusty 0x8000 for all the roms which are paged, and each rom has it's own little bit of 4k RAM further up which is paged in with it. The rest of the address space is mapped in through an eprom so I can have better control over things like sticking the vias in zero page efficientlyxn I was going to use logic gates for the addressing, but decided against it for simplicity

User ram starts at about 1k (there's 31k of it in 16 paged areas), another experiment. if it doesn't work then I'll just tie it down to 31k.

There's a header for arduino shields. In paticular GameDuino looks interesting as it's VGA out and supports OpenGL as well as other accelerations and it's also an open hardware project, so all the docs are online. This is something to look at once the board is working though

A fair bit of work also went into the power regulation, including power fail detection, so there's a few cycles of NMI to at least not to mess things up before the rest of the system runs out the door (and also crowbar protection against overvolt/ reverse polarity - a hard lesson learned from recently killing an icom7300 which costs a bomb and has no form of overvoltage protection at all)

And there's lots of leds, and bargraph leds! and an LCD!

[whartung]

piemmm wrote:

A yes on the schematic (once I've found out if it's working or not - I want to find out myself if I messed something up badly )

If you post the schematic now, there may be a chance someone here can tell you more about whether it will work or not. Catch things you might not have.

[BigDumbDinosaur]

whartung wrote:

If you post the schematic now, there may be a chance someone here can tell you more about whether it will work or not. Catch things you might not have.

That's true. Other eyes often catch things that the designer might not be seeing.

I do see something about the physical PCB layout that might cause a bit of trouble. There are a lot of filled planes in between traces and furthermore, it appears they are not grounded. Grounded fill planes on the top and bottom layers are usually poison to good AC performance. Ungrounded planes are even worse, as they act like antennae and radiate noise all over the place. Filled planes serve no purposes in a digital device except to muddy up waveforms. I'd get rid of them if it were my design.

Now, inner layers are a different matter...

[Arlet]

Quote:

Grounded fill planes on the top and bottom layers are usually poison to good AC performance

That's a bit strong. I make all my boards with ground pour on top/bottom layers, and I've never had a problem, even at 100 MHz frequencies.

I do agree that you want to avoid disconnected islands. The first step would be to place the traces so they don't needlessly cut the planes into pieces, and second step would be to stitch top and bottom planes together with vias. Also, make sure the traces, vias and clearance are set correctly so you don't have overly big gaps.

Anyway, I don't expect this board to fail because of the ground pours.

[piemmm]

Hi!

Yes on the ground planes - it's only the top pour which didn't get grounded (the bottom one did). The board is already in the process of getting fabbed and I'm not to worried at this point about it, but yes the next version will be fixed (and better checked for that) as well as all the improvements I've learned from the first iteration

I'll post the schematic once I've finished working out all the bits I did wrong . - I mainly want to do this because it's actually fun doing the learning part for myself, though I do appreciate the offers for help!

Boards should take a few days before they come back, hopefully before the end of next week, then it's soldering and coding time!

[piemmm]

Boards arrived today - lots of checking to do then lots of soldering!

[GaBuZoMeu]

Looks good!

And you've got two boards - so you got a second chance

Good luck and much fun with it!

[Dr Jefyll]

GaBuZoMeu wrote:

Good luck and much fun with it!

The boards looks great! I second what GaBuZoMeu said!

piemmm wrote:

lots of checking to do then lots of soldering!

Hmmm. It's understandable if you're eager and are feeling inclined to do all the soldering at once. But you might want to consider a staged approach instead, as follows. First do only what's needed to get the 5 Volt supply working (and see that it does work). Next solder only what's needed to run a NOP test (ie, CPU in place but no memory or I/O), which will let you verify that the address & data buses are free of shorts. Then solder and (again using the NOP's) verify that the memory decoding is working as planned. And so on. At each stage do only what's needed for the next test.

In the event of a problem there's reduced risk you'll have to un-solder anything (as may be necessary to access the traces under an IC socket).

Congratulations on your project!

Jeff

[BigDumbDinosaur]

Dr Jefyll wrote:

piemmm wrote:

lots of checking to do then lots of soldering!

Hmmm. It's understandable if you're eager and are feeling inclined to do all the soldering at once. But you might want to consider a staged approach instead, as follows...

I'll second what Jeff suggested. That's the approach I use and it's never failed me.

[piemmm]

Yep, those are excellent suggestions and the proper way to do it

Unfortunately not the road I'm taking this time... Important logic is socketed though, and will be fairly straightfoward to debug (have most of the kit to do this fortunately). The only big issue is if I need to do track mods (it's a 4 layer board) though there are ways around that too for the prototype.

Ran out of parts for the moment, the rest of the PSU side and missing chips come next week from mouser so hopefully I will be able to post more progress here once I've done that (unless you think I should move it to another thread, which is fine just let me know). I'll post more as I get things working and also any 'learning' mistakes