I'm gathering ideas for the computer I want to build, was wondering what you all thought of the idea of using some N82S123N 32x8 bipolar PROMs for address decoding? They've got 5 addressing inputs, and 8 tri-stated outputs, access time is supposed to be ~45ns.

I'm probably going to be looking at a 1MHz clock to start off, but I might go to a faster CPU later, am I correct in thinking these proms would work with one of WDCs 14MHz chips?

Pros? Cons? Any other ideas for other uses for them besides address decoding?

The reason I'm considering using them is that I aquired a small surplus supply of them a while back (apparently they used to use them for cellphone NAMs). This will be a personal project, just a one off computer, so availability isn't an issue.

I'd need to build a programmer, but that shouldn't be a problem.. I've already got information on doing that. I'd probably make one that plugs into the 44 pin edgecard connector on my old VIC20 (did that with a 2732 programmer I built.. worked out well..)

> am I correct in thinking these proms would work with one of
> WDCs 14MHz chips?

No. Remember that the 6502 does a complete read or write in half a clock. In fact, the Apple II did two memory accesses per clock: one for the processor and one for the video, so they could both access the same memory, seemingly at the same time, at full speed. One clock at 14MHz is about 70ns, so half is about 35. Your EPROMs would take more than that before even considering the access time of the memory and other parts. Granted, the address and R/W do become valid before phase 2 goes up, but you need to gate the RAM with phase 2, not just the address. With quick glue logic, RAM speed with a 14MHz 6502 should be no slower than 25ns, and probably faster. The 14MHz ones will operate a lot faster however, if the parts connected to it are fast enough.

Those new to the microprocessor sport tend to make address decoding much more complex than it needs to be. This leads to lots of extra parts (and build time) and long propagation delays. As a contrast, the address decoding at http://www.6502.org/users/garth/project ... chematic=2 can be done with nothing more than a quad NAND gate (74xx04) and supports 32K of ROM and 16K of RAM, and up to ten I/O ICs (like 6522's and 6551's). With a small change, you could have 32K of RAM and 16K of ROM, and still allow for more I/O than you could want.

I've been studying the WDC65C02 timing specs and here is what I calculate for your configuration:
CPU address setup - 30ns
Address decoding - 35ns (your PROM)
Ram memory access 70ns (assuming a 70ns part)
read data setup time 10ns
Total access time: 145ns

Based on that, your max clock speed could be 6.8Mhz.

However, as others have stated, the timing specs are worst case, so you could possible go faster if you follow good construction practices.

Daryl

Not exactly true.

Remember that RAMs have /OE, /WE, and /CS signals. Therefore, /CS can be driven by the address decoder output independently of the phi2 clock signal. Only /OE and /WE need be qualified by the phi2 signal.

Therefore, it is possible to get a 14MHz part to work with a 50ns RAM in this case, provided you have nothing accessing the bus during phase 1.

Ok yes, I guess I did simplify it almost to the point of lying. I see there's more I need to look at. See if you find this to be correct. I got out a databook for a Samsung 55ns 32Kx8 SRAM, and it shows the time from OE\-true to data-valid being 25ns, if the address and CS's have already met their minimum times. So, for a 14MHz 65c02, which specifies a minimum data set-up time of 10ns, you add 25ns in this case, plus the 15ns max for 74HC04 or 'LS04 for a simple inverter to go from phase 2 to the SRAM's OE\ input, and you have a total of 50ns, for a total phase-2-high time, meaning 100ns total clock cycle time, which means 10MHz with 55ns SRAM. Again, that assumes the other minimum times for address and CS set-up are met. But the W65c02 data sheet says the processor's address set-up time could be as much as 30ns, leaving only 20 more ns (assuming the same glue-logic propagation delay that we used for the OE\) for the SRAM's address set-up time at 10MHz, and it needs 30, not 20. So if everything is at max times, the 55ns won't work at 10MHz either.

OTOH, if the CS is the limiting factor instead of the OE\, then for a 14MHz 65c02, which specifies a data set-up time of 10ns and an address set-up time of 30ns, you can add the memory access time, let's say 55ns since it's a standard that's close to your 50, plus let's say 15ns for simple address decoding, bringing us to 105ns, or about 9.5MHz-- if we go strictly by the data sheet, which we already know has some problems, since it sometimes implies that the part can't work anywhere near as fast as the reports say it can.

thanks guys, I've forgotten a lot in 20 years.. lol.

I think I'll stick with a 1MHz clock, I also have a bunch of kinda slow(150ns) 8Kx8 SRAMS, so I could use some of them for my first project and then do a whole 'nother design with a faster clock from scratch later on.

Microtan did something similar on their 6502/6809 SBC board using a 74S288 BiPolar PROM. Bags of flexibitily, a bit of a bugger trying to work what combination of PROM data and link settings were needed for a given memory map. And the CPU clock circuit was very fussy about which make of 74LS04 it would work with.

Happy days those.....