Yes, I'm still interested if it will help you with the QUART. I'm glad to hear rev 1 is coming along. I've done some reading up on the QUART datasheet and see the many errors and omissions. I may not be able to solve anything, but thought a fresh set of eyes might help.

Daryl

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POC version two, revision one (POC V2.1) is now a paper computer, which is the fastest and most reliable kind of computer currently available. The I/O layout has been revised, but functionally this is the same machine as POC V2.0.

Here's the schematic:


Here is the printed circuit board layout:


Significant circuit changes relative to POC V2.0 are:

• Replacement of the NXP 28C94 quad UART (QUART) with two NXP 28L92 dual UARTs (DUART). This change functionally emulates the QUART but gets away from the QUART's obstreperousness. The timer in DUART 'A' acts as the jiffy IRQ generator, while the timer in DUART 'B' is currently uncommitted, but could be used in a role somewhat like that of the HPET in current x86-64 hardware. A gain with the 28L92 is its larger transmit and receive FIFOs, 16 bytes versus 8 with the QUART.
  
  
• Replacement of the MAX248 octal transceiver (PLCC44) with two MAX238 quad transceivers (SOIC24). This change was made primarily to simplify the layout of the PCB around the TIA-232 "harmonica" output jack, and has no performance effect. Although the combined footprint of the two MAX238s and their charge pump capacitors exceeds that of the MAX248 and its capacitors, routing with the MAX238s proved to be less difficult.
  
  
• Removal of the inverted reset function from the ATF1504AS CPLD. Every one of the CPLD's I/O pins was in use in POC V2.0 and I needed another pin to provide a chip select for the second DUART. The irony is the 1504 is maxxed out as far as I/O pins goes, yet only about one half of the total logic resources are in use.
  
  
• Addition of a gate to generate the inverted reset that used to be an output from the CPLD. The DUARTs are operated in Intel bus mode—actually easier to interface with the 65C816 than Motorola bus mode, which means they require an active high reset. The SCSI host adapter also requires an active high reset.
  
  
• Addition of a triple-input AND gate to drive the 65C816's IRQB input. A concern was how the wired-OR IRQ circuit would behave with the addition of another interrupt source, due to an expected increase in total parasitic capacitance. As a lazy IRQ circuit could cause spurious interrupts, I decided to change things around.
  
  The three inputs of the AND gate are connected to the three possible interrupt sources: the two DUARTs and whatever is plugged into J5, the expansion socket. The gate itself is physically placed in close proximity to the DUARTs and J5 to minimize trace length and parasitic capacitance. A resistor network is placed in close proximity to the AND gate and provides the pull-up voltage for each input. The AND gate's output drives the 65C816's IRQB input through a longish trace. The gate can sink or source 24mA, which means the parasitic capacitance of the connection to IRQB should not cause any grief.
  
  
• A pull-up resistor was added to the DUART X1 clock generation circuit to conform with the 28L92 data sheet (page 62, figure 17). NXP doesn't offer an explanation as to why the resistor should be there, but since resistors are inexpensive and I have lots of them in the parts pile, no reason not to add it.
  
  
  Attachment:
  File comment: NXP 28L92 Data Sheet
  28L92_dual.pdf [336.96 KiB]
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• Reversion of the expansion socket hookup to that used with POC V1.1. I did this primarily to allow me to continue to use the SCSI host adapter I developed for use with V1.1

I also tinkered with the PCB's mechanical design in several ways:

• The board size is now 6 inches by 4 inches (152 mm by 102 mm). POC V2.0's PCB was 6 inches by 3.5 inches (152 mm by 89 mm) so I could use Express PCB's Proto-Pro service, which is limited to 21 square inches (135 square cm), and a maximum of 650 holes (pads and via). During the layout of POC V2.1, I substantially exceeded the 650 hole Proto-Pro maximum, which meant I would have to use Express PCB's production service, which has a board size limit of 168 square inches (1083 square cm) and essentially no hole limit. Given that, I decided I might as well increase the board size and make things a little easier, especially since I will be going to a different (less expensive) board house to get the PCB made.
  
  
• The 65C816 and the two CY1049D static RAMs are in closer proximity to each other. Doing so reduced the length of many of the traces connecting the SRAMs to the '816 and eliminated some via.
  
  
• The Ø2 clock generator components were relocated. I was seeing some ringing in the signal and surmised that the length of the connection to the CPLD might have been a possible cause. The new layout reduces that trace's length by about one half.
  
  
• An extra mounting hole was added at the bottom left corner. The new hole appears to be redundant, since there is one right above it, immediately below the "harmonica" jack. The mounting hole by the "harmonica" has to be there to attach the SCSI host adapter—whose mechanical layout conforms with that of POC V1—however, that is the hole's only purpose. The new hole at the bottom left corner will be responsible for supporting that corner of the board.

I'm going to sleep on this design for a few days and then return to it to see if I overlooked anything or made any mistakes.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Without any attempt to offend or criticise your work - just some thoughts which came to my mind looking at the layout and memory map:

1. It looks to me as if your current layout have enough space to use a 68pin ATF1504. Perhaps this could be beneficial, saving some extra logic and perhaps add some more features.

2. I am playing a bit with the W65C265. Its I/O is placed @$00:DFxx. That is were you places your HMU. If you would condense your I/O space to that page (perhaps possible with the 68pin ATF) your POC and the 265 became more compatible. Of course, as I don't know what you intend to apply to "expansion XIOA/XIOB/XIOC" this suggestion might be inappropriate.

The PLCC68 version of the ATF1504 is not a stock item. Currently, Atmel (Microchip) requires a 100 piece minimum order for that item.


I have no interest in the 65C256, nor can I envision any possible use for it.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

And you probably won't went into "mass" production
Squeezing in an 84pin ATF1508 (socketed) could be difficult if not impossible...

Anyway good luck.

Not likely. POC V2 is a stepping stone to a more powerful future design. Hence I'm not in a rush to fit the machine with a big CPLD.


Actually, it can be done. See attached PCB layout for a design that I scrapped.

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Wow !

But it's quite large and you started to rearrange alot. Hope it's worth all these efforts.

But perhaps then you could gain more benfits out of this huge CPLD, like SPI e.g.

Good luck!

As I said earlier, POC V2 is an intermediate design intended to test a number of theories I've concocted. The above design was not really practical because it only had two serial ports. As you can see, much of the PCB real estate was consumed by that PLCC84 package.


I don't know that I will implement SPI in any of my designs—I haven't found any use for it, but I eventually hope to have SCSI built in, instead of on a plug-in host adapter, as I do now. I also want to implement a console port that can work with just a VGA monitor and standard PC keyboard. POC V2's console port circuitry has been designed so it can drive a serial terminal, as I am now doing, or a terminal adapter, which is one of the projects waiting on me to get back some of my eyesight.

Where the large CPLD's resources might be useful is in rigging up some sort of DMA controller. I still have a lot to learn about writing CPLD code before I will get to that point.

Eventually I want to be able to scale up the serial hardware up to eight ports, along with the console and software transfer port, and also have a machine architecture that can support a preemptive multitasking environment. Combined with the SCSI interface, which opens the door to high capacity mass storage, I would have a true general purpose computer that could actually do useful work. All of this is discussed at length here and on my website.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Well it seems as if PLCC-68 is a dying package

I only found three speed variants of EPM7064LC68 @ Mouser still available - but pretty expensive. And of course its Altera/Intel, so perhaps you would need a different design software...

That seems to be the case with CPLDs.


Those items are all obsolete and the only reason Mouser continues to list them is they have inventory. In any case as you noted, different development software would be required.

It appears that Microchip will continue to produce the five volt Atmel CPLDs for some time to come. The ATF1508AS is quite powerful and is available in several small-outline packages, which would reduce PCB footprint. However, such packages are a challenge to solder, currently beyond my abilities.

I'm hoping that Microchip will give the WinCUPL development software a badly needed refreshing. The current version of the compiler-simulator, 5.30.4, is nearly 15 years old and crash-prone.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

As I earlier posted, I slept on the PCB design for revsion 1 and decided I could do a better job of compacting the layout. Here's what it looked like after moving around one or two things:


The major changes are the relocation of the TIA-232 port "harmonica" jack and the MAX238s. The extra mounting hole at the bottom left corner is gone, as is the corner in which it was located, and the board is a little smaller from top to bottom. There are no functional changes to the circuit. I may make some further changes to the board layout, but I think this is substantially like what it will be when it is built.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

That's a fine layout and having all external wirings on one side is something I like.

If it does matter to save 5 mm:

You can move U13 between the NMI and RST string and move the complete section right to the center screw holes 5.08 mm upwards - only your POC label is slightly touched by J6.

If you then rotate J6/RN6 clockwise and move them above U3 (now your label needs to be rearranged) but the space where they were should be sufficient for Y2, C14, R2.

The RST-LED can easily moved, U4 could rotated or you may use a single gate package (SOT.23-5).

Thanks for the suggestions. I originally had U13 where you proposed, but relocated it after printing the layout actual size and seeing how easy it would be to accidentally hit the device with the little screwdriver I use to short out RST or NMI when needed. Of course, I may one day rig up some pushbuttons...


Doing so puts Y2 too far away from U10 and results in the X1 clock signal having to be snaked through the phalanx of traces around JP2 and JP3.


It could, but the incremental savings of PCB real estate wouldn't be worth the trouble. Also, I am incapable of working with an SOT23 package—I only have visual acuity in one eye.

All of my PCB layouts have to stay within my ability to see and work with small parts. As miniaturization is not a goal of my activities, I concentrate on concocting a workable design that I can assemble.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

At least they would prevent searching for the screwdriver and/or driving the pins under your nails

You mentioned this nastiness elsewhere - I wish you succeed in ameliorate your visual acuity somehow. Knowing this causes me to delay my suggestions as I could imagine that packing everything more densely isn't really helpful now.

Nevertheless I wish you good luck with POC V2.1 ! I'm sure you will report your progress so we can participate a bit.

That little screwdriver has been laying on the desk next to my POC setup for about eight years. It's not going anywhere anytime soon.


I've been in the second phase of a clinical trial since October of last year in which a medication is being tested that, it was hoped, might repair the problem (cystoid macular edema). So far I haven't experienced any improvement worth noting.

This POC V2 topic has been running for some six years, for a while in parallel with my older POC V1 project's topic. I try to document what I'm doing in some detail, although not to the point where a lot of marginally useful posts are generated. Also, POC V1 is still being played with. In fact, right now both POC V1.1 and POC V2.0 are connected and running.


Note the trusty screwdriver next to the one logic probe.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!