What if independent MOS Technology had survived?

[litwr]

It is possible to dream about the development of our beloved 6502 in the case that MOS Technology continued independently. Let's call these improved 6502 the 6502+. I can suggest the next steps which could keep 6502+ leadership up to the end of the 80s.

1) 1976 - the elimination of zp,X page warp. This step would allow the direct stack addressing.

1) 1977 - the elimination of empty cycles. This would make 6502+ 25% faster. This was done with 4510 but only in 1988. This step might also include the addition of several useful minor instructions like BIT#.

3) 1978 - the addition of the second accumulator. This would make 6502+ up to 100% faster.

4) 1979 - moving part of the zero page short addresses into registers. It might be 4 or 8 bytes, for example, starting at $80. The long (2 bytes) address to zp would be used for an access to zp RAM. This would increase 6502+ speed up to 50%.

5) 1980 - more zp to registers and the addition of byte by byte multiplication instruction like at 6809.

6) 1981 - the support for 16 MB memory addressing with the introduction of an mode register and an address mode bit in it. 6502+ would fetch 3 bytes for any address in 16 MB mode and 2 bytes in the old 64 KB mode.

7) 1982 - more zp to registers and 16 bit ALU. 16-bit mode would be provided by another bit in the mode register. 6502+ would fetch 2 bytes instead of one for the operations with data. Stack and index registers and accumulators would become 16 bit in this mode. Zp-registers would also become 16 bit. This would reduce the number of zp-registers by half. 6502+ would become 50% faster with 8 bit data bus and 100% faster with 16 bit. It is possible to imagine 8 bit index registers in this mode like at 65816. So it would possible to use the additional bit in the mode register for this opportunity.

8 ) 1983 - all zp to registers and the addition of word/dword by byte/word division instruction and a barrel shifter. This would increase the speed of arithmetic many times.

9) 1985 - 32 bit ALU. It's easy - just use a bit in the mode register. We would have A, B, and 64 zp 32-bit registers.

10) 1986 - a paged MMU like at 80386 or 32016.

11) 1987 - a possibility to simultaneous execute two instructions and use proper pipelining. This would increase speed up to 50%.

12) 1988 - 32-bit address bus and the index registers.

IMHO this architecture would be faster than even mighty ARM or Intel 80486 at 1991.

[Arlet]

Would all these steps be backward compatible ? And how would the opcode space be affected by each change ?

[GARTHWILSON]

Look into the 65816 which came out in 1983. It has most of these things you mention. It runs my '816 Forth two to three times as fast as my '02 Forth runs, for a given clock rate. It's easier to program than the '02, makes for denser code (even though it has a 16MB address space), and has a lot of added capabilities.

[Arlet]

The 65816 still has zeropage and no extra accumulator or index registers, so it's missing steps 3, 4 and 5 already.

[BigDumbDinosaur]

GARTHWILSON wrote:

Look into the 65816...has a lot of added capabilities.

Most importantly, it currently is in production.

[BigDumbDinosaur]

Arlet wrote:

The 65816 still has...no extra accumulator...

Sure it does.

[Arlet]

I assume that "extra accumulator" means that it has the same capabilities as the first one, so the 65815 wouldn't qualify.

[GARTHWILSON]

Quote:

The 65816 still has zeropage and no extra accumulator or index registers, so it's missing steps 3, 4 and 5 already.

#3. It has accumulators A and B, which when optionally combined, make accumulator C, a 16-bit accumulator.
#4. You can use 16-bit index registers as address registers, for example LDA 0000,X where X is a 16-bit address. The 0000 can be replaced with an offset.
#5. The '816 has the address range to use large look-up tables for a lot more than just multiplication, resulting in much, much better performance than a 6809.

Quote:

I assume that "extra accumulator" means that it has the same capabilities as the first one, so the 65815 wouldn't qualify.

You can do XBA to exchange the two, and do the needed operations on the other accumulator with the same instructions and same capabilities, then XBA again if desired.

Still, the 6809 failed to perform much better than the '02, in spite of its richer instruction set and programmer's model, which means the '816 would far outperform a 6809 at a given clock speed. Additionally, the 65's have reached clock speeds one to two orders of magnitude higher than that of the 6809.

[Arlet]

Quote:

Still, the 6809 failed to perform much better than the '02

That's a different issue. I'm just saying that the 65816 doesn't follow litwr's list.

Quote:

You can use 16-bit index registers as address registers, for example LDA 0000,X where X is a 16-bit address. The 0000 can be replaced with an offset.

Correct, but it's not the same as item 4, which would add an extra register. And presumably, that extra register could be used to produce a (REG), Y addressing mode, because it's meant to replace zeropage.

[GARTHWILSON]

It won't be exactly the same; but I did say the '816 "has most of these things you mention." (Plus, it has other benefits not mentioned.)

[Arlet]

The 65816 has a couple of them, but the ones that are missing are vital stepping stones to further changes on the list. Most notably, you can't do pipelining while still dealing with zeropage (edit: maybe you can, but it will be much more painful).

[Tor]

All those steps on different years would mean a new CPU every time.. which is probably exactly not what would happen. Instead, there would probably not be any of the Commodore "oh we need something special for a one-off - go ask the hw designers to make yet another variant of the 6502".
For (external) customers, predictability is what matters. Or at least that was true for a long time. These days I wonder. I can't even figure out how many AVR variants there are - there's an app on my phone with page after page of AVR / Atmel variants. I can't sort them out. Something similar is going on with Microchip. Which means that I don't buy any of them, as a hobbyist, and I don't look there professionally either. (Well, they are microcontrollers, so most of the differences are probably in what i/o etc. they have - but still. Way, way too many.)

[Arlet]

Tor wrote:

All those steps on different years would mean a new CPU every time

Hence my question whether these steps would be backward compatible. If not, then few people would accept a new architecture every year, or couple of years.

[GARTHWILSON]

The PIC16's (after 16C5x IIRC, which had only a 12-bit instruction word which I never used instead of the 14-bit like the other PIC16's) all had the same instruction set until the PIC17's were eliminated from the lineup and their extra instructions seem to have shown up on the 16F1's. The 12's are just 8-pin versions of the 16's, and the 10's are even smaller versions of the 16's, using the 16s' instruction set. The PIC18's are pretty much the same thing plus jury rigs tacked on to make up for some of the shortcomings of the 16's. The 24's and 32's are entirely different architectures, as I understand it. I've only used the 16C, 16F, and 12C ones, all with the same instruction set but a different combination of I/O modules. Even with those though, if you want an 8-bit A/D converter, it works the same way on all the ones that have it. Same with PWM, synchronous-serial ports, etc., so you don't have to re-learn things from one to the next. Don't the AVRs have more or less the same story? (I don't know anything about the AVRs.) Anyway, it would have been great if the '02 or '816 got firmly entrenched in a nice lineup of microcontrollers. As for instruction-set upgrades, doing it incrementally will obviously require backward compatibility. If performance is really so important (for many applications, it's not), it seems to me that every decade or so, the thing to do is toss the backward compatibility and revamp the whole thing, even though you still keep the same basic programmer's model and assembly language, and just add to it. I'm sure the '816 could have been quite a bit better if it didn't have to run '02 code.

Quote:

Most notably, you can't do pipelining while still dealing with zeropage (edit: maybe you can, but it will be much more painful).

Dual-port memory might make things interesting if you want to address both main memory and the direct page at the same time.

The 65CE02 got rid of almost all of the dead bus cycles, and had 31 op codes that executed in a single cycle, unlike the 2-cycle minimum of other variants. It had a lot of other nice attractions too.

[Arlet]

Quote:

4) 1979 - moving part of the zero page short addresses into registers

Would these zp registers also get more operations, such as an ADD with a zp register as destination ?