Hi all

I have led around with Verilog, but much. Recently though, I was considering the idea of implementing a complete C64 system on a FPGA.

The FPGA development board have in mind is in at this link:

https://za.rs-online.com/mobile/p/progr ... s/1346451/

Highlights of the board:

- 33280 logic cells in 5200 slices (each slice contains 4 x 6-input LUTs and 8 x flip-flops)
- 1800Kbit Fast Block RAM
- VGA video output

My question: Does anyone know if the number of logic components/slices available would be enough for implementing the following for a C64 system: 6510 CPU, 2 CIA chis and a VIC-II

My 6502 core uses 133 slices on an older Spartan 6 (also has 4x6-input LUTs), so I guess that 5200 slices is more than plenty for a complete C-64 system.

Thanks Arlet!

I'd estimate the board has more than enough logic resources (a C64 guestimate is <4000 slices).
CRT controller chip VIC-II with a scan converter worked out to about 1000 slices (4,000 6-LUTs) for another project I worked on.
The amount of memory on the board (225kB) is limited but should be more than enough. I think the C64 uses 64kRam + 20k? ROM. So there should be about 150kB available to implement a scan converter.

_________________
http://www.finitron.ca

Just for information, for this purpose and for anyone else, that there is a thread noting various affordable FPGA dev boards over here:
viewtopic.php?f=10&t=1787

Also, the first post of that thread links to a survey of available boards.
https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards

(I notice that this Basys 3 Artix-7 FPGA Trainer Board is not mentioned in the thread. But it is mentioned in the survey, at $150 price point.)

I'm not familiar with the C-64, but what does it scan converter do that requires so much memory ?

It really wouldn't need much memory. There's a dozen or two registers, some internal counters, and about a dozen bytes of sprite info that it needs to hold. I think the "about 150kB available" is just that, availability, not that the system needs that much.

_________________
WFDis Interactive 6502 Disassembler
AcheronVM: A Reconfigurable 16-bit Virtual CPU for the 6502 Microprocessor

It took me so long to write a response that White Flame responded first.

I did not mean to imply that the scan converter would require 150kB of memory.
A scan converter might not be necessary at all if the output is NTSC/PAL compatible. The VIC-II chip has very specific timing that's tied to the old TV standard and a 1MHz bus.
How much memory is required depends on the implementation of the scan converter. The scan converter could be simple or complex depending on desired display output capabilities.
If the converter can be made to operate in sync with VGA frequencies then it's only necessary to buffer a line or two of display pixels. I've seen a scan converter that simply uses double the VIC-II horizontal and vertical frequencies for display in standard VGA format (640x480).
If the VICII output frequency is not in sync with the VGA frequency then the whole screen may need to be buffered. That will take a lot more memory but may still be doable with 150kB. (I buffered the whole screen with my design so that an 800x600 VGA timing could be used).

_________________
http://www.finitron.ca

With a modern VGA monitor, I don't think you have to worry about generating the exact frame rate, so just doubling the pixels would be good enough.