Hallo allemaal,

Can anybody tell me what the level of the individual flags is after a reset?
It seems I simply cannot find this info in the books I have :(
Thanks!

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Ruud,

On page 11 of the current WDC 65C02 datasheet, the flags setting after reset are decribed. Here is what it shows:


I take this to mean that the hardware sets the B,D& I flags but its up to the software to configure the N,V,Z&C flags.

Daryl

Well Ruud, this has been said before: If the datasheet doesn't cover some issue, it is.. err... literally undefined. You can safely assume it is for a reason.

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I trust my somewhat flawed English is comprehensible to all.

Many thanks!

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Hi Ruud,

To quote the original MOS 65xx Hardware Manual :

"It should be assumed that any time the RESET line has been pulled LOW and then HIGH, the internal states of the machine are unknown and all registers must be re-initialised during the restart sequence".

When dealing with IRQ it states :

"Until the various registers in the processor have been initialized, the processor is not able to respond properly to any external interrupts. For this reason it is important that the system RESET disable all external interrupt signals until they are enabled by the processor".

So it would seem that if there is any chance of the code being run on older variants of the 6502 than WDC's, it is prudent to start your reset code with SEI.

ghaytack, I don't have a MOS data sheet, but my oldest 6502 datasheet is a Synertek one from 1979, and it does say that the reset sequence sets the interrupt disable bit before loading the reset vector. I think that in your quote above, they're probably just explaining why they do that, saying that if they didn't, even if your first instruction in the reset routine in ROM is SEI, you might still get into trouble if the interrupt line is being held low, because the interrupt vector could be taken before you even get to the SEI. All the interrupt types, including RST I'm sure, set the interrupt-disable flag.

Hi Garth,

It puzzled me as well not finding any mention of it in the MOS hardware manual (it's labelled Frist Edition, August 1975) as I was fully expecting to find it. Other data sheets I looked at last night (Rockwell, CMD) state that RESET disables IRQ in the CPU and I've always written code on that basis since I started 6502 coding with the Lance A Leventhal "6502 Assembly Language Programming" book.

A 1978 edition of the Rockwell R65xx Programming Manual states it explicitly and appears to be a reprint of the MOS 1978 manual with a different cover. An early oversight by the MOS documentation department perhaps (to go with the mistakes in many 6522 data sheets)?

George