handyandy wrote:
I would think that since a 65816 emits a bank address on the data bus that's the reason for the high impedance so as not to interfere with an apple IIc's video cycle (perhaps).
That might have been the thinking, but the 65C02 shipped with the Apple ][c did not have that characteristic, nor did the 65C802. Generally speaking, the 65C family stays on the buses at all times unless the
BE input is driven low, at which time
A0-A15,
D0-D7 and
RWB go to the high-Z state.
Quote:
8 and 16 bit instruction set is probably another way of saying emulation and native mode.
Except there is no such a thing as an eight and 16 bit instruction set, and the instruction set has no relation to operating mode. The
m and
x bits in the status register determine if a load, store or implied register operation (e.g.,
INX) operates on eight or 16 bits, but the actual instructions are the same in either case.
It's important to understand that all 65C816 and 65C802 instructions are valid in both modes, although with some limitations in emulation mode. For example,
SEP works in both modes, but the
m and
x bits cannot be changed while in emulation mode, preventing the selection of 16 bit registers. Certain instructions, such as
TCD and
TSC implicitly operate on 16 bits regardless of operating mode. Also, the B-accumulator remains accessible in emulation mode through the
XBA instruction.
It can be said that in emulation mode, 65C816 sort of becomes a 65C02 in terms of software, but almost looks like an NMOS 6502 to other devices on the buses, except the bank bits are emitted during Ø2 low. In terms of software, the real 65C802 was the same as the 65C816 in emulation mode, but accurately produced the 65C02's bus characteristics.
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The diagram is flawed, IMO. But if there's other evidence to say a 65c02 (or any 65xx processor other than the '816) can drive the data bus in phase 1 then I'm all ears. 
