WDC are preparing to launch another W65C265 board. This time it seems to be just the micro controller on a PCB with high and low speed oscillators and 8 output LEDS. There is no external RAM or ROM so you just have the built in monitor and 578 bytes of on board RAM.

http://wdc65xx.com/w65c265qbx-mensch-microcomputer-educational-sbc/

The board has 28 pins broken out to connectors. When I get time I'll check if these would allow a larger memory attached. If it does I might get one.

Still a bit pricey compared to an Arduino or ARM board and without some extra RAM you can't write anything other than a tiny assembly application.

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Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

Seems like you can, seems like to can deselect the on board stuff, and the major signals are out on the pins.

Interesting there's no on board flash that I can see.

It's an '816 core, they have a 16MB memory map.

Would be nice to be able to easily wire up a 1MB RAM, and some Flash, and still retain the USB power/serial connection.

Curious lack of other interfaces. Just raw ports. No SPI, I2C, first class USB. Certainly no networking or block storage.

Always curious who the market is for something like that, particularly today with massive following the Arduino and RPi families have.

I'll be amazed if this unit gets significant of sales. The "instant gratification" generation, used to the Arduino and Pi hardware, is bound to find this unit too spartan to be interesting.

On another but related tack, I personally fail to see a market anymore for any WDC microcontrollers. The 65C256 might have a chance if it weren't for being bogged down with a mask programmed ROM, limited I/O flexibility and limited clock speed. For less money, more powerful and flexible hardware can be gotten. It's a simple choice for the average designer.

I think if WDC wants to continue to penetrate the hobby market they need something more than what they have been offering. Whatever it is, it should be equipped with lots of RAM, a decent sized ROM for firmware, and a mix of WDC and non-WDC I/O hardware. Just my curmudgeonly opinion.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

It's not only the Pi and Arduino. In a few days, SiFive is supposed to start shipping the first RISC-V SoC, the HiFive1 (see https://www.crowdsupply.com/sifive/hifive1 and https://hackaday.com/2017/01/05/hands-o ... ontroller/). It costs US$59, and the RISC-V ISA seems very clean, comes with SPI, and will work with both 5V and 3.3V. Oh, and it runs at 320 MHz.

I'm not sure this is a board for me, with just 16 kB RAM (can't tell if I can even access that for programs or if this is a Harvard machine), but I assume more and more RISC-V stuff is going to follow, given the open model.

If you can add external memory, and the price is right; it might be worth using as the core of something bigger.

WDC is just milking this old cow until it dies. There is no way that WDC can hope to compete on the microcontroller market with the likes of NXP, STM, or Microchip.

That's exactly it. And it sounds fixable. Mask programmed ROM in this day and time makes no sense and can't compete with anything. I/O and clock speed must be fixable too.

I don't think there was any milk to be had anymore from old Bessie. They essentially have two viable products: the 65C02 and the 65C816. The 65C21, 65C22 and 65C51 are woefully out-of-date and all but irrelevant in today's market. Neither of their microcontrollers has anything to offer a modern designer. That cow is dead on its feet.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I'm afraid it's beyond fixing. Pretty much everything in the chip is outdated compared to modern microcontrollers, including the CPU core. Plus it's very expensive too. Basically, they would have to scrap everything they have, including their current design team, and start from scratch.

Does anyone have noticed a bug (?) in the timing specs for the W65C265S ?

The current DS http://archive.6502.org/datasheets/wdc_w65c265s_sep_13_2010.pdf stated "Static to 8MHz clock operation" (pg.3, Key Features).

Page 43 lists the "AC Parameters", right side headed with "VDD=5V +/-10% 8 MHz". But when you look down to tCYCF its minimum should (only) be 250ns - what is 4MHz or am I totally stoned??? Btw. this corresponds to e.g. tISA (22ns) + tODA (90ns) + tR or tF (15ns) = 127ns = tCYCF/2.

Could it be that this wasn´t noticed so far?

It probably has been noticed. WDC's documentation is famous for its errors and omissions.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

I suspect that it isn't intended to compete with the Arduino. If it is, someone at WDC has gone nuts on the quiet, or is seriously out of touch.
It looks to me like it's intended to help get people into low-level programming. I don't mind the goal, but the execution really needs to be better to carry it off.

Am I reading the schematic correctly, only A0-A15 are available on the pins ?

Yes, A16-23 are not connected to anything in the schematic and the pins used to provide chip selects to external RAM are driving the LEDS. You should be able to fill all of bank 0 with SRAM (except the I/O page $DF) and it would appear replicated in all other banks (other than pages $00,$01 and $DF which are on-chip in bank 0 only).

I quite like the 65C265, it needs a just a few support components to build working system compared to the 65C816. At $30 this board is bit expensive and a bit limited. I think I would rather buy the device direct and put it in a board of my own design with a faster crystal (8Mhz) and a lot more SRAM.

_________________
Andrew Jacobs
6502 & PIC Stuff - http://www.obelisk.me.uk/
Cross-Platform 6502/65C02/65816 Macro Assembler - http://www.obelisk.me.uk/dev65/
Open Source Projects - https://github.com/andrew-jacobs

I was wondering if maybe the 65c265 presents A16-A23 on the data bus at the beginning of each cycle, in addition to on the dedicated pins (either because it was designed that way, or because it inherited the functionality from the 65c816). I couldn't find any mention of this in the documentation for the 65c265.

Even with only 16 address pins available from the board, it could be viewed as a breakout board for the 65c256, and it should be trivial to use it with up to 64kB of external memory.