GaBuZoMeu wrote:
May I asked what "It does not work" means more specifically?
If the QUART generates an interrupt, issuing an "update current interrupt register (CIR)" command should cause the CIR to be loaded with a byte that indicates the interrupt source, channel number, etc. It doesn't happen. I ruled out the device being defective by substituting another QUART...same results. This tells to me I do not have the device correctly configured, am not understanding how the interrupt arbitration functions work, or there is a time lag from when the command to update the CIR is issued (it's a dummy write to a specific global control block register) until the CIR contains valid data.
A timing issue is a theoretical possibility, as everything that goes on in the QUART is slaved to the 3.6864 MHz X1 clock. Assuming the instruction to read the CIR immediately follows the instruction to update the CIR, only four Ø2 cycles will elapse between the two operations, which could be too fast for the QUART (however, I/O accesses are wait-stated, which does give the QUART more time to respond). However, I think I may have ruled out timing, as I've tested for that by placing some NOPs between the "update CIR" and "read CIR" instructions. That had no apparent effect.
Quote:
Within the TX part I´m not sure how
Code:
.iirq230 lda #nxpcrtxd ;tell UART to...
sta (tiacr,x) ;disable transmitter
works - which control register is written?
Location
TIACR is a set of four direct (zero) page pointers to the command registers of the four channels within the QUART. Earlier in the code,
.X was loaded with a channel offset (channel index × 2, where the channel index is 0, 1, 2 or 3). Writing the value
NXPCRTXD to the command register disables the transmitter. There is a corresponding value that when written into the command register enables the transmitter.
The use of indexed indirect addressing to access chip registers, such as in the above code fragment, has been tested and verified on the 28L92 DUART in POC V1.1.
Quote:
As far as I have looked into the datasheet, perhaps using the IMR to suppress IRQs from an empty TX may be an easy way.
Suppressing the TxD IRQ is no easier from a programming standpoint than disabling the transmitter, as the IMR in each block of the QUART controls both transmitters in the block, as well as the RxD IRQs, change-of-state IRQs, etc. Each channel's command register is independent of the others', so no special provisions must be made to disable or enable a specific transmitter. Fiddling with the IMR means keeping track of its current state in a shadow register so the settings of the other interrupt sources' bits are preserved when one specific interrupt source is disabled or enabled—the IMR is write-only, so instructions such as
TRB and
TSB can't be used..
Quote:
I agree the documentation is ... well it´s a complex circuit and that should cause a very clear structured manual. But such things are rare, very rare.
Data sheets widely vary in quality. For example, the SCSI host adapter I designed for POC V1 uses the AMD 53CF94 bus controller. This device is substantially more complicated than the 28C94 QUART, yet was less challenging to get working, due to a well-written data sheet. If the 28C94's data sheet was as well written as the 53CF94's data sheet we wouldn't be having this discussion.