BigEd wrote:
Interesting detail Jac! We had another case to worry about: a write to a peripheral using an indexed addressing mode (as you are using a 'C02 you're fine.) In our case, interfacing with the Beeb's NMOS 6502, this case means we can get two consecutive accesses, and it's the second one which is important. So, after a read access, we have a quick look to see if chip select is still active. This cost a bit of performance when we were doing the bit-banging in the ISR.
I suppose if it would be necessary to check for two consecutive accesses to the same address range, it would probably be possible to do an extra address check in the second clock cycle and postpone the internal house keeping by one more cycle. In the case of the Apple 1 PIA emulator on the Propeller, it wasn't necessary.
There's just one flaw in the PIA emulator in L-Star currently: the reset circuit can't be emulated because the Propeller isn't connected to that line (there aren't enough I/O pins), so it can't reliably determine whether the CPU is accessing the direction register or data register. Because of this, you always see a character 255 on the output when WOZ Mon initializes the port for output. I could work around this by trying to detect a reset sequence (the 65c02 reads 3 decreasing addresses on the stack, followed by a read of FFFC/FFFD) but it's not that important. For now, I just pretend that the control register and the direction registers don't exist.
===Jac
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