I seem to be encountering conflicting information about how the zero flag (and other flags in the processor status register) are set. On the one hand, I've read that the zero flag is set when the accumulator becomes 0. On the other, I've read that it's when any arithmetic/logic instruction generates a zero result, even if that result isn't going into the accumulator (for instance, if it's being written back to memory instead of being put in the accumulator). So, which one is it? Thanks in advance.

I'm not sure it's either of those, precisely. I wonder if there is a succinct and accurate way of stating it. Both transfers (to A, X or Y) and ALU operations can set zero - including CMP and BIT, which produce results which you don't see. Is that everything? (By transfers I mean loads, Txx, and PLx.)

Several emulators have come unstuck with TXS, I think. It's a transfer, but not to A, X or Y.

Off the top of my head, Z and N are set in the same circumstances as each other. V and C are set by arithmetic, and C by shifts.

Beware: many references will have one or two errors. Probably including this very reply!

(BTW, you might enjoy this neat diagram by Bob Sander-Cederlof entitled "The 6502 Programming Model" although it doesn't answer questions like this.)

An automatic compare-to-zero instruction is built into the following 65c02 instructions: LDA, LDX, LDY, INC, INX, INY, DEC, DEX, DEY, INA, DEA, AND, ORA, EOR, ASL, LSR, ROL, ROR, PLA, PLX, PLY, SBC, ADC, TAX, TXA, TAY, TYA, and TSX. This means that, for example, a CMP #0 after an LDA is redundant, a wasted instruction. The only time a 65c02 (CMOS) needs a compare-to-zero instruction after one of these is if you want to compare a register that was not involved in the previous instruction; for example,

(Note the Y and the X are not the same register.) If you can spare a register to which you can transfer the one you want to test, you can save a byte with the transfer instead of a compare instruction. The example above, if the contents of A don't need to be kept, could be changed to:

and then you can branch on the N or Z flag which tell if X was negative or zero. The TXA isn't any faster (both TXA and CPX# take two clocks), but TXA takes only one byte, whereas the CPX #0 takes two bytes.

The NMOS 6502 did have a bug in that the flags weren't always correct after a decimal-mode operation like ADC, so then you might have to follow it with the CMP #0 to get the N and Z flags right. It's best to just use the CMOS processor.

This is from the Tips For Programming the 65(c)02 page of my 6502 primer.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The book, "Programming the 65816 including the 6502, 65C02, and 65802" is indispensable. It it very thorough, with this kind of info and lots more. No 6502 enthusiast should be without it. Seriously. You can get it at http://65xx.com/Products/Programming-Manual/ .

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

Ah - good catch on decimal mode! See Bruce, again, at
http://www.6502.org/tutorials/decimal_mode.html#4.1

Loading registers affects status flags. Changing registers affects status flags. Changing memory affects status flags, but there's a caveat.

STORING (STA/STX/STY) memory does NOT affect status flags, but instructions such as INC/DEC/ASL/LSR/AND/OR/EOR (list not exclusive) do affect status flags. BIT doesn't change anything but status flags, same with CMP. RTI clobbers the status register, along with PLP. Popping the stack does, as its similar to loading a register.

Branches, Jumps and JSRs have no effect.

So, basically, I would consider that anything that changes memory or registers affects status flags, save for STA.

Good catch on RTI and PLP! I think CMP and BIT show that your last sentence doesn't quite capture it.

It might be personal preference, but I'd rather have a few simple rules, or principles, than a catalogue of details. After all, when programming, we don't generally need to look up which operations affect flags. I think that's not because we've internalised a list, but because we've grasped the underlying principle.

When R-M-W instructions change memory and change the flags, it's not the storing back that changes the flags, but the ALU operation which takes place before storing it back. ST_ (even STZ), PH_, and TXS have no effect on the flags. Nor do the branch operations, or JSR or JMP or RTS.

_________________
http://WilsonMinesCo.com/ lots of 6502 resources
The "second front page" is http://wilsonminesco.com/links.html .
What's an additional VIA among friends, anyhow?

The general rule is any operation that produces a zero result sets the Z flag in the status register. This includes loading any register with zero, incrementing or decrementing a register or memory to zero, performing a logical operation that produces zero, etc.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

I haven't even thought about the subject (at least in the case of the 65xx family) for many years, because its flag setting behavior so perfectly matches my natural thought processes while I'm coding. No other CPU comes close in that regard (except my own designs), and it causes me to always second-guess myself when coding for a different processor, thinking that I'm missing an important optimization.

Mike B.

Yikes! That sounds bad. Better high-tail it to the ER! We don't need any dead members.

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!

EOR ($50),Y ?? [/deep_inside_joke]

Mike B.

Code:

          LDA #CHOLESTEROL
          ADC #PIZZA
          AND #BEER
          EOR #SCOTCH
          BIT #THE_DUST
          STA HOLE_IN_THE_GROUND

_________________
x86?  We ain't got no x86.  We don't NEED no stinking x86!