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Except that since I'm using dual port RAM, the VIC-II almost never needs to steal CPU cycle in order to gain access to the RAM, since in my setup, the VIC-II has its own dedicated RAM port.
This will be a separate thread, but for now here is the summary.
At startup, the system does in fact run at 1MHz with the VIC-II generating the CLK for everything. A logic circuit latches the clock signal and routes the data where it needs to go. There is a transceiver that connects the CPU with the ROMs, the VIC-II, the SID(s), and the CIAs. When the VIC-II needs to read the RAM, because it has its own dedicated ports, it does not need to steal CPU cycles. The exception is that if the CPU is attempting to read or write to a ROM, or any of the IO chips at the same time as the VIC-II is reading, in which case the CPU is halted until the process is completed. Again this halting will only occur if those two things are happening at the same time. Otherwise, since the CPU has its own RAM port it can do its own thing.
Now as you recall, the 6510 has some IO pins (P0-5) that enable ROM banking and cassette port communication. I have a circuit that mimics that feature, only mine adds two more pins (P6&7). One of these when switched high will enable turbo mode, which basically tells a logic circuit to decouple the CPU (and everything on the fast side) from the 1 MHz clock and instead couple to the 20MHz clock. The VIC remains master of the slow bus. At this point however, if the CPU attempts to access a ROM, SID, CIA, or VIC-II register, the CPU is halted, then re-coupled to the 1MHz clock again. The CPU completes its access, then it is decoupled and switched back to the 20MHz clock.
I am still working on this latching system and the logic that will control it. That will be its own thread. I know it's complicated, but it should still function. I may loose a cycle here and there during the switches depending on how synchronized things happen to be, but those missed cycles should not be a major issue so long as things are timed so that data isn't lost.
As far as I can tell from going through this process, the two busses can be though of as operating separately with a common RAM access and a form of forced synchronization when needed. And to minimize slowdowns, some things can be done. For example, if I read the ROMs and copy them to RAM, I can then bank the ROMs out. Then when those routines are accessed, they can execute from RAMat full speed. Then the CPU only has to slow down for IO access.
The approach I'm taking will be mostly transparent to the software. If I try to write a VIC-II register for example, as soon as the CPU outputs it's address lines, and a positive address match occurs, then the CPU is halted using the RDY pin. Then the 20MHz clock is decoupled and the 1MHz clock is swapped in. When the clock is in the right phase, the RDY signal is released and the CPU will complete its operation. Once the cycle is complete, the RDY pin is held again, the 1MHz is swapped out with the 20MHz clock, and when the clock is in the right phase, the RDY pin is released.
I am not opposed to some type of phase locked loops, or having one chip handle all the logic functions. And generating all the signals from the VIC-IIs clock output. Alternately I can also do it from the VIC-IIs 8MHz input.
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I am working on building a 65816 based computer (for personal use)
Eventual goals include:
65816 CPU up to 14-16 MHz (In Turbo Mode)
up to 16MB RAM (512K on the main board)
Dual YM3438 audio
IEC serial device support
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