DerTrueForce wrote:
This is a collection of features that I think would be desirable for a 16-bit 65-series processor....
This sort of discussion regularly comes up and has almost as many permutations as there are active members on the forum.
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The starting point for this design is the WDC 65C02.
Why?
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A, X, and Y registers are 16-bit full-time.
They already are in the 65C816. All that happens when you set the
m and/or
x bits is make them look like eight bits to the outside world.
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24-bit address space, address pins are not multiplexed.
That would be a very useful feature. The MUXing of A16-A23 onto the data bus in the '816 was something that was done to make the '816 appeal to Apple. It certainly was not an elegant thing to do. The irony is the '816 could have A16-A23 separately brought out if it was in a PLCC52 package.
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8-bit data path (To simplify the wiring and the width-switching)
Already part of the '816. Two memory cycles are used to load/store words.
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Two new opcodes for bigger operations: WIDE, which makes 8-bit instructions into 16-bit ones, and LONG, which extends addressing.
WIDE might be useful, but I fail to see any use for
LONG. In the '816, long addressing is implicit with the
$Fx set of opcodes and the
[<dp>] and
[<dp>],Y addressing modes. Having to set up 24 bit addressing mode with another instruction sounds like a performance killer to me.
Incidentally, one of the best features of the 65xx family is the use of three character instruction mnemonics. That size makes for a very efficient method of looking up mnemonics. If mnemonics vary in size, as you are suggesting, the look-up function now has to account for that, and a simple index and compare algorithm becomes one of using a pointer table to the mnemonic list in the assembler.
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Math and bitwise logic operations are always done on all 16 bits, but the N, V, C, and Z flags are set to correspond to the width of the instruction being executed.
Already the case with the '816. Again, the
m and/or
x bits determine that in the '816.
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No decimal mode or emulation mode.
Eliminating emulation mode would make the MPU's design easier, plus remove the
XCE instruction, freeing up its opcode for something else. Eliminating decimal mode would be a significant loss of functionality in my opinion, as decimal mode is quite useful for converting between the ASCII representation of numbers and their binary equivalents.
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Relocatable Stack and Direct Page(a la '816).
Register swap and STP instructions from the '816.
Good.
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No shared interrupt vectors(BRK seperate from IRQ).
Already the case with the '816 in native mode.
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No clock outputs or /SO, as these are generally not used these days(as far as I know).
They don't exist on the '816 and their use on the 65C02 has been deprecated.
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COP software interrupt and output pin.
COP already exists in the '816 and causes
VPB to go low during cycles 7 and 8, which can tell logic that an interrupt is being processed.
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built-in reset circuit with pushbutton(essentially an integrated DS1813).
Not necessary. To quote the '816 data sheet:
2.25 Reset (RESB)
The Reset active low input is used to initialize the microprocessor and start program execution. The Reset input buffer has hysteresis such that a simple R-C timing circuit may be used with the internal pull-up device.
The DS1813's main value is that it senses the level of Vcc and will wait until Vcc exceeds a certain threshold before starting its reset cycle. The need for that feature depends on what else is attached to reset.
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Problems:
Exactly how LONG works with the indirect addressing modes.
Where to put the vectors?
Exactly how this works.
Since this hypothetical MPU doesn't have to be compatible with any other member of the 65xx family, I would suggest putting the reset vectors as high in RAM as you can get them to create the maximum amount of contiguous address space.