Disregarding the four JTAG pins, you will have 32 pins to connect into your circuit. Four of those pins are input-only and the remaining 28 are input/output. You will need clock and reset inputs, which you connect to GCLK1 and GCLR, respectively. That leaves you with two input-only pins and 28 input/output pins for the rest of your circuit.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Those CPLDs can be very confusing, so I thought I summarize my experience with these ATMEL CPLDs.

There are a total of 36 user pins on a ATF1504AS in either the TQFP-44 or PLCC-44 package. Out of these pins some can have a special function.

The pins named TMS, TMO, TMI, TCK are the JTAG interface, if you want in-circuit programming, or if you don't have a programmer that natively supports the ATF1504AS you must not use these pins. If you have once loaded a design that makes use of these pins you need a programmer that supports the ATF1504AS natively. Something that first is not really documented by AVR (the ones listed are no longer available) and if you find one then they are extremely expensive (the cheapest one I have seen with native support for ATMLE CPLDS was sold new for 495USD). A JTAG Programmer is less than 70 USD.

This leaves you with 32 user pins.

Out of these 32 user pins 4 can only be used as INPUT. Now these inputs can have different functions as well. Either they are used as normal input then the rules regarding FAN-IN explained below will apply. On the other hand if your design requires a function that can be described as CLOCK, CLEAR or OUTPUT ENABLE you should use these pins as CLOCK, CLEAR or OUTPUT ENABLE input. The advantage of using these pins is that they can be routed globally. What this does is that these functions are available to all macro cells without using the input multiplexor of a macro cell block. Note the ATF1504AS supports up to 3 global CLOCKS, one global CLEAR (or reset if you prefer) and two global OUTPUT ENABLE.

Then there are 3 IO pins that can also have some other functions, IO/GCLK3 for example can be used as the third global CLOCK, else it is a normal IO pin. PD1 and PD2 are power-down pins and can place the chip in a power-down mode where it does keep the state of it's output pins but will reduce the power consumption. You need to toggle these pins to wake up the chip again. However PD1 and PD2 are features you need to select, else these pins are normal IO pins. I have never used the power-down feature.

So for standard hobbyists you have 4 INPUT only pins and 28 IO pins.

Now some words about fitting a project into the CPLD. The ATF1504AS has 64 macrocells divided into 4 logic blocks of 16 MCs. And that's also the source of problems. Even there is a global bus that carries all signals (inputs and feedbacks) you can only feed 40 signals into a logic block, this is the function of the signal input multiplexor of each logic block. This is called FAN-IN. You should look at the fitter report and then you will see which signals are selected for each logic block. Most of the time the limit I have encountered are due to the limited FAN-IN and not to the number of macrocells. Note that when you make use of the global CLOCK, CLEAR or OUTPUT ENABLE feature these signals will not count for the FAN-IN of a logic block. That is the reason that you should make use of that feature as often as possible, I think all of my project have at least one CLOCK, one CLEAR (reset) and one OUTPUT ENABLE.

Cheers

Peter

Thank you for the detailed information!

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Cat; the other white meat.

I was wondering how these devices compare to the Altera MAX 7000, assuming you were using a similar size part? My main (only) reason for preferring them is that they are supported by the relatively decent Altera software, and the easy to come by USB programmers. The problem is the part is not current, and they are quite hard to obtain in PLCC44.

There's also the Xilinix XC9572, available in PLCC44. These are again, sadly, obsolete but still obtainable. If you want to use these CPLDs you need to use a slightly older version of the Xilinx software, and the programmers are a little pricier then the Altera programmer, but these are still very useable parts in our micros.

I really wanted to try out an Atmel CPLD but I found the software impossible to find, and the programmers hard to find too. What software and programmer should be used? Can you use VHDL, or Verliog are you limited to ABEL? Looking at the Atmel website it seems you have to pay for the software?

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8 bit fun and games: https://www.aslak.net/

The software can be downloaded from Atmel's website at no charge. You merely fill out a form and then download and install.

As for programming, the ATF15xx CPLDs have a JTAG port, which is easy to integrate into your design, using a standard 10 pin header (see pic). A relatively inexpensive programmer can be purchased from a number of sources that will allow you to attach the JTAG port to your PC. It's not difficult.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

Aha. Thanks. Is that a full suite, or just a WinCUPL "compiler"? Can you use VHDL or Verilog? I'm really "attached" to using VHDL for my programmable logic and don't want to learn something new just for the sake of the vendor.

I found this: http://www.atmel.com/tools/PROCHIPDESIGNER.aspx which I'm guessing is a VHDL/Verilog compiler but it says you need a "two year license".



Sure; my last two SBCs use the same 10 pin JTAG header. Atmel lists programmers that they sell for 60 USD, but you are saying I can use a "generic" programmer? Assuming I'm stuck with USB, where can I get one? What software would I use to drive it? With the Xilinx and the Atmel parts it is all integrated and therefore seems much more straight-forward.

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8 bit fun and games: https://www.aslak.net/

The WinCUPL package consists of an editor, compiler and simulator. A separate piece of software, AtmelISP, is run to actually program the device via JTAG.

CUPL is a logic programming language that was developed from ABEL during the 1990s. WinCUPl is an adaptation of CUPL to Windows. I suppose you could use Verilog or VHDL, but you'd have to install a different compiler. I have not investigated doing so with Atmel's PLDs, as I have found WinCUPL adequate for my needs.


That's correct: you will be spending money for it.


I believe Kanda sells something, but I'm not familiar with it. The parallel port version of Atmel's programmer is what I have and it works like a charm with POC V2's JTAG port.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

You need a ATDH1150USB-K JTAG interface. This is the only AtmelISP compatible USB programmer. I'm as well stuck to USB so I also purchased this one from Kanda https://www.kanda.com/products/Kanda/ATDH1150USB-K.html and it works like a charm and it really is not expensive. I have programmed both ATF1504/8 successfully.

I've been re-reading this. This has been very helpful.




Pardon my ignorance, but this part confuses me. From what I understand, each pin needs to be a part of a macrocell. Meaning if you had 10 pins each running their own logic, that would need 10 macrocells. Even though the logic might be very simple. If you had something like a databus, then 8 pins could be apart of one macrocell.

Is that correct?

If so, where does the 40 signals come in? Are signals the same as pins in this context?

I *really* wished there was a "CPLD for Dummies" book because I sure am a dummy sometimes.

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Cat; the other white meat.

Each output pin requires 1 macrocell, so an 8 bit databus requires 8 macrocells (at a minimum)

Ah. So, that's bi-directional...right?

Meaning my databus would require 8 macrocells and not 16 macrocells?

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Cat; the other white meat.

Yes. You can declare any given pin to be an input, output, or bi-drectional, using the appropriate logic statements. I do that with D0-D4 in POC V2's CPLD.

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x86?  We ain't got no x86.  We don't NEED no stinking x86!

A macrocell is somewhat like a big programmable gate with a large number of inputs and one output that can be sent to a pin. If you declare an input pin, you can send that input to a number of macrocells, each responsible for a single output or a single internal flip-flop.

I asked ATMEL once for a PROCHIPDESIGNER license (there is an option to get it free) because some designs I made would not compile under WinCUPL. But instead they gave me some support how to change the design so it will work with WinCUPL. So I found out there are many options in WinCUPL so even complex designs will fit. I decided to stay with WinCUPL. Sad thing is that WinCUPL is only poorly documented. PROCHIPDESIGNER would have the advantage to support VHDL/Verilog, but there are some remarks to that, again documentation is very poor and I doubt that it supports all the new development in VHDL design as the software itself is no longer developed.



I also wished there would be some Introduction Guide. So here the next chapter in my experience with CPLDs. First a word about the different brands. CPLD are very similar and differ only very little from brand to brand. As long as you stick to the basics in your logic you can use whatever CPLD in a PLCC-44 package. Generally all CPLDs have the following structure, here I'm referring to the 64 MC size (or 72 MC in case of Xilinx ones). Larger CPLDs are similar and mostly are just multiple 64/72 MC CPLDs in one package.

As I have explained in my first post you have user pins. MC are numbered from 1 to 64 and are grouped into logic blocks. Logic Block A consists of MC 1 to 16, Logic Block B consists of MC 17 to 32 and so on. Each of the user pins that is IO capable has a fixed MC associated with it. But only if you use this pin as an output or a bidirectional PIN the MC will be effectively "connected" to this PIN. Macro Cells are the equivalent to the OLMC (Output Logic Macrocell) of GALs, however a typical MC of a CPLD only has 5 product terms (in contrast to 8 to 16 PT of a OLMC in a GAL22V10). As I have already explained we have a total of 36 user pins out of them 4 or input only pins. So half of the macrocells is directly "linked" to a IO pin (which includes the JTAG pins). So in fact in a standard hobby design there are 28 MC that are linked to pins and the rest are "buried" MCs.

A macro cell has 5 product terms, a flip flop and some signal routing features that allows the mapping of the PT to some special functions. Which parts are used depends on your design. When you look at a logic block then you have essentially a GAL with 40 inputs, 16 OLMCs and up to 8 outputs (this is valid for PLCC-44 and TQFP-44, in case of larger packages more outputs per logic block are available but you still have only 64 MCs).

Then you have the signal routing. This is different to GALs. In a CPLD you have a global bus that carries all possible signals. That is all pins (IO and Input only pins), all outputs of MC (regardless if they are buried or if they are one of those with a linked PIN, so this is quite some signals, well over 100). For each Logic Block you can select up to 40 of those signals to be used in the Logic Block. So to speak these 40 signals are a subset of all possible signals. This is called the FAN-IN of a logic block. Each of those 40 signals are then available to all 5 PTs of every MC in a Logic Block. If I say select then this is not really something you have to do. Normally the fitter automatically selects which signals are faned-in. It also performs the mapping of your signals to the PINs if you let him do so (i.e. if your PIN definitions do not specify the PIN number to be used). Something I recommend when you first build your design. Of course once you have done the layout of your board you need to fix the PIN numbers to avoid the shuffling of PINs when you change your design on a life system. For this you need to copy the PIN number findings of the fitter to your design files.

Note that the global input pins like RESET, OUTPUT ENABLE or CLOCK (if used) are available to all MCs and do not count as signals used for FAN-IN. As FAN-IN is one of the most limiting factors in a CPLD you should make use of these features as much as possible.

Now back to the MC and its 5 PTs. You may think this is not much, but when you look at your design, or even take designs you have done using a GAL you will find that only very few outputs require more then 5 PTs. Also there is a nice feature in CPLDs. A MC can borrow the PT of its predecessor MC if this MC is not linked to a PIN or if the predecessor MC is not used. E.g. PIN 6 of the PLCC-44 is linked to MC 11. MC 6,7,8,9 and 10 are buried or cannot be used (MC 8 which is PIN 7 which is TDI of the JTAG interface must not be used) and are all predecessor of MC 11 (that is adjacent MC with decrementing number). So you can borrow up to 40 PTs. But borrowing works only for one logic statement. But again this is hardly a limitation.

Now how are PTs used. Each MC has a PT MUX and each PT can be routed to one of the functions of the MC. A MC provides the following functions you may use.

CLOCK if you need one or more PT for the logic of the clock of a Flip-Flop, else you should use the global CLOCK input
RESET if you need one or more PT for the logic of the clock of a Flip-Flop, else you should use the global RESET input
OUTPUT ENABLE if you need one or more PT for the logic of the tri-state out, else you should use the global OUTOUT ENABLE input
Asynchronous Reset of the Flip Flop
Asyncrhonous Set of the Flip Flop
Normal Logic Function use either for a directly connected output (no FF used) or for the D input of the FF

Note, only the logic function may borrow PT from predecessors.

This is very simplified. There is more, e.g. each MC has a local feedback bus that allows to use combinatorial outputs within the same Logic Block without consuming FAN-IN. This is useful in case you cannot borrow PT from predecessor MCs. But there is a propagation delay penalty to it.

I hope I did not add to the general confusion of CPLDs and rather shed some light to it. Just download WinCUPL and start to convert your GAL designs to WinCUPL and have a look what happens. You could for example first create the JED for a GAL and then remove all PIN numbers and tell WinCUPL it should create the files for a ATF1504AS using the same logic. If course this will be a total overkill but you get a chance to understand what WinCUPL does how MCs work. The best is to start with a complex design made for a GAL22V10 with all features of a GAL22V10 used that are not generally available to smaller GALs to really see what's going on, e.g. a Design that uses CLOCK, OUTPUT ENABLE, RESET and SET features.

Cheers

Peter

I've discovered some useful information about the ISP versions of these devices as I've been using them for my ROM X product (http://www.theromexchange.com).

It IS possible to use the JTAG pins as general I/O by adding the following property to your source :

PROPERTY ATMEL {JTAG=OFF};

With that in there, the code should compile, the fitter should then re-use the JTAG pins as you intend, and create a .JED file for programming. Once programmed (you'll be prompted to set the JTAG Port Check Override option in the ATMISP options menu), the JTAG will be locked out, but you've got 4 more pins to play with!

Now, if in your design you ensure that you can isolate the OE1 pin on the CPLD from any other circuitry (so that you can safely apply +12V to the OE1 pin without blowing the crap out of anything attached to it!) then you can re-enable the JTAG port in this manner. Applying +12V to the OE1 pin through a resistor (1k8 is fine) whilst attemting to reprogram the chip in ATMISP should yield results. I initially get a verify error, but after that the JTAG is unlocked again and usable

I suppose you also best ensure that nothing is going to be driving the JTAG pins while you are programming the thing else include links (jumpers or smd resistors etc) to disconnect other circuitry from the JTAG pins.

Anyway, this may possibly free up some pins for you.

Secondly, it is also possible to develop for these devices in VHDL or Verilog using Altera's Quartus software (web editiion 13.0sp1 is the last one to support the MAX 7000 series chips on which the ATF1500 series devices are based) - you select the equivalent Altera device :

EPM7032 = ATF1502
EPM7064 = ATF1504
EPM7128 = ATF1508

Once you have compiled your design (.POF file generated) you can use Microchips POF2JED utility to convert it to a .JED file for programming via ATMISP