|/ E S T R E L      Copyright (c) 2006 Samuel A. Falvo II
|\    2 P 1         Preliminary Material -- All Rights Currently Reserved

===================================================
Kestrel Bus Architecture Specification Revision 1p1
===================================================
                            I D E A   D R A F T   3

Features:
* Microprocessor Independent Bus
* Supports a flat 24-bit address space
* Supports partial address decoding for true plug-n-play support
* Fully asynchronous design
  * Minimal logic required for synchronously clocked bus masters
  * Use combinatorial or monostable multivibrator logic for
    acknowledgement generation
* 8-bit data bus for economy of implementation

Minimum Implementation
======================

            as      as
Pin:        Slave   Master
------------------------------------------------------------
_reset      I*      I*          Kestrel Hardware Reset
_irq        O*      O*          CPU Interrupt Request

a(0..23)    I       O           Address Bus (16Mi sub-space)
_we         I       O           Asserted when sending data to slave
_ss16       I       O           Asserted when addressing slot space
_start      I       O           Asserted to start a transfer
_end        O+      I+          Asserted to acknowledge a transfer
d(0..7)     I/O     I/O         Data Bus

_br         O       O           Bus Request signal
_bg         I       I           Bus Granted signal
------------------------------------------------------------
LEGEND:
    I   Input
    O   Output
    *   Open-collector; may be driven by bus master, bus slave, or
        backplane circuitry.
    +   Three-state.  Driven only by addressed bus slave.
    I/O Three-state input and/or output signal.  Direction depends on
        _we.
------------------------------------------------------------

Bus Slave Operation
~~~~~~~~~~~~~~~~~~~

The d() signals are used to carry data from or to the master, depending
on the state of _we.  When _we is high, the flow of data is from the
slave to the master.  Otherwise, the flow of data is from the master to
the slave.  d() is considered invalid unless both _start and _end are
asserted, as part of a fully-interlocked handshake.  See below.

The a() signals provide addressing information.  24 address lines
provides 16,777,216 bytes of address space.  How this address space is
mapped into a computer's memory space is not specified officially, but it
is intended to be directly mapped into the CPU's address space to make
maximum use of its bus mastering capabilities.  Others may prefer to
provide a small, 256-byte window, with a register to 'bank switch' the
I/O space accordingly.  Still others will provide a smaller window via a
special 16-bit pointer register, and maybe a data register that, upon
access, optionally causes the 16-bit pointer to post-increment.  Note,
however, that these latter two approaches compromise the utility for
supporting multiple bus masters.

The _ss16 signal is asserted when the current bus master is attempting to
reach a specific slave's dedicated I/O space in the 24-bit address space.
With A(20..23) being set to an implementation-defined value addressing a
1MiB window of dedicated I/O space for all slots, and bits A(16..A19)
indicating the slot number, this leaves only A(0..15) for addressing
peripheral chip data.  Therefore, when _ss16 is asserted, use only the
lowest 16 address bits for further address decoding.  For example, the a
computer may place its I/O space at $F00000-$FFFFFF, so that
$F00000-$F0FFFF is slot 0, $F10000-$F1FFFF is slot 1, etc.

If _ss16 is negated during a bus cycle, but the current address is
referring to a peripheral that exists on the card (e.g., an address which
is set via a programmable base address register, for example), the
peripheral may still respond, as the address bus is assumed to be fully
decoded.

NOTE:   The bus makes no attempt to avoid bus contention when used in
        this mode, and therefore it is assumed that all base address
        registers are programmed in accordance with address space
        allocation policies determined by the computer's operating
        system.  The operating system is ultimately responsible for
        properly allocating unmapped device address space.

        To do their part, peripherals must fully decode all pertinent
        address bits, starting with A(23) and on down.  They must also
        communicate the address range requirements to any host operating
        system as well.  This must be done via the card's dedicated I/O
        space.

_start is asserted after the address, control, and optionally, data buses
have become stable.  This officially begins the bus transaction.

_end is asserted by the peripheral in response to the assertion of
_start.  It is the addressed slave's responsibility to make sure enough
time elapses between the falling edge of _start and the falling edge of
_end.  For example, 70ns RAM should have 70ns of delay from the falling
edge of _start to the falling edge of _end.  It is also the slave's
responsibility for keeping _end asserted for any recovery time of the
addressed peripheral as well.

Read/Write Timing
-----------------

            ______ _________________________________ ___
_we/a()     ______X_________________________________X___
            ___________                              ___
_ss16       ___________\____________________________/___
            ____________________                      __
_start                          \____________________/
            ______ ...............         _________ ___
d(r)        ______X...............>-------<_________X___
            ______ ............... _________________ ___
d(w)        ______X...............X_________________X___
            __________________________________         _
_end                                          \_______/

Bus Master Operation
~~~~~~~~~~~~~~~~~~~~

_br is asserted by the device whenever it desires access to the bus.
_br may be asserted asynchronously.  This signal may also be negated at
any time, indicating that the device no longer needs access to the bus.

_bg is asserted or negated by the bus arbitration unit on the backplane
or motherboard in response to the assertion of _br.  The bus
specification provides no guarantees on response times of any kind -- it
depends on the algorithm of the arbiter, along with what other
peripherals currently are using the bus at the time.

When asserted, _bg indicates that the device will become the master at
the end of the CURRENT bus cycle if one is in progress.  Likewise, when
negated, it indicates the device will cease to be the bus master at the
end of the current cycle.  Note that the bus arbiter is free to implement
any bus fairness algorithm it chooses -- peripherals MUST expect the
condition where _bg may be negated at any time, even if _br is still
asserted.

If the bus master negates its _br signal, but the _bg signal remains
asserted for longer than expected, the master MUST continue to assume it
owns the bus for as long as _bg remains asserted.  Dummy, idempotent bus
cycles are recommended to prevent bus lines from floating for an
excessive period of time.

Bus Request Timing
------------------
            ________
_br                 \___________________________________________________
            ________________________
_bg                                 \___________________________________
                                                  ______________________
_start      _____________________________________/
            __________________                           _______________
_end        __________________\_________________________/
                                                             ___________
own         ________________________________________________/

            The bus request unit of a bus master first waits for _bg,
            then waits for the current bus transaction to come to a
            completion before officially accepting ownership of the bus.
            _own is a signal local to the bus master to indicate that it
            officially has the bus.

If the bus arbiter decides to rescind the bus grant prior to the device
becoming the bus master, then the device cannot assume ownership of the
bus until the _bg signal is re-asserted.

                        _______________________________________________
_bg         ___________/
                                    ___________________________________
_start      _______________________/
            _____                          ____________________________
_end        _____\________________________/
            ___________________________________
own                                            \_______________________

            Note that the condition of _br is immaterial for releasing
            the bus.  If the bus arbiter rescinds ownership of the bus to
            a peripheral, that peripheral MUST tri-state its bus
            transceivers at the completion of whatever bus cycle is
            currently in progress.

Interfacing the 6502 to the Kestrel Bus
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

There are no plans to officially support the 6502 processor architecture
at this time.  The 6502 lacks the ability to wait on write (use of FIFOs
for rate-matching writes was encouraged back when it was designed), thus
compromising the asynchronous bus protocol detailed above.  Furthermore,
it lacks sufficient addressing space, thus requiring external banking
registers.  This, in turn, results in the inability to effectively use
bus mastering technology.

Interfacing the 65816 to the Kestrel Bus
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

The 65816 is quickly and easily interfaced to the Kestrel Bus.  Below is
an ASCII-art schematic for the interface circuit:

    + indicates OR gate
    -1 indicates inverter
    * indicates AND gate


              +---+        (E)
    vpa >-----|   |       +----+
              | + |---*---| -1 |o--------------> _br
    vda >-----|   |   |   +----+
              +---+   |
               (A)    |   +---+
                      +---|   |
   phi2 >-----------------| * |o----+
    rdy <-------------*---|   |     |
                      |   +---+     o
                      |    (B)   +-----+
                      |          |  s  |
                      |          |    Q|o--*---> _start
                    +-----+      |  r  |   |
                (D) |  *  |      +-----+   |
                    +-----+    (C)  o      |
                     | | |          |      |
                     | | |          |      |
                     | +------------*----------< _end
                     |   |                 |
                     +---------------------+
                         |
                         +---------------------< own


NOTE:   Implemented in a PAL or PLA chip, this logic should not incur
        excessive propegation delays, thus allowing the CPU to be driven
        at or near its rated speed without incurring wait-states.

OR gate A is used to detect when the 65816 is attempting to perform a
legitimate bus access.  Its output will go high when this happens; the
inverter E will condition the signal to be used as the _br signal on the
bus.  Note that asserting _br does NOT guarantee the 65816 will actually
get ownership of the bus!

NAND gate B is used to detect the start of a new bus cycle.  This occurs
when phi2 goes high AND RDY is asserted from the previous bus cycle AND a
legitimate bus cycle is being requested.  If these conditions are all
true, it will set the flip-flop C, which brings _start low to assert it.
The immediate feedback from _start to the AND gate D will cause RDY to
negate only a few nanoseconds later, thus guaranteeing the 65816 will see
a wait-state condition if the peripheral doesn't respond in time.

It should be pointed out at this time that the 65816 can only drive the
_start line when it owns the bus.  Therefore, the _start signal above is
an internal signal that must be tri-stated when it doesn't own the bus,
just like other addressing signals.

At this point, the CPU just waits for _end to be asserted by the
peripheral.  When it does, it will cause the flipflop to reset, bringing
_start high.  Note that AND gate D will still have its output negated at
this point -- thus ensuring a premature bus cycle completion doesn't
happen.  To complete the bus cycle, both _start must be high AND _end
must be high.  Once the peripheral negates its _end driver, AND gate D
will ensure that RDY goes high, thus terminating the 65816 bus cycle.

This circuit assumes that the 'own' signal is locally generated once
proper bus ownership has been detected.  See the section above on bus
request timing.

If the 65816 lacks ownership of the bus, then the _end signal can be
delayed as required, thus ensuring bogus data isn't read or written,
until the bus ownership can be re-established.

    A       B       C
+-------+-------+-------+
|  gnd  |       |  Vcc  |   1
+-------+-------+-------+
|  gnd  |       |  Vcc  |   2
+-------+-------+-------+
|  a0   |       |  a1   |   3
+-------+-------+-------+
|  a2   |       |  a3   |   4
+-------+-------+-------+
|  a4   |       |  a5   |   5
+-------+-------+-------+
|  gnd  |       |  gnd  |   6
+-------+-------+-------+
|  a6   |       |  a7   |   7
+-------+-------+-------+
|  a8   |       |  a9   |   8
+-------+-------+-------+
|  a10  |       |  a11  |   9
+-------+-------+-------+
|  gnd  |       |  gnd  |   10
+-------+-------+-------+
|  a12  |       |  a13  |   11
+-------+-------+-------+
|  a14  |       |  a15  |   12
+-------+-------+-------+
|  a16  |       |  a17  |   13
+-------+-------+-------+
|  gnd  |       |  gnd  |   14
+-------+-------+-------+
|  a18  |       |  a19  |   15
+-------+-------+-------+
|  a20  |       |  a21  |   16
+-------+-------+-------+
|  a22  |       |  a23  |   17
+-------+-------+-------+
|  gnd  |       |  gnd  |   18
+-------+-------+-------+
|  d0   |       |  d1   |   19
+-------+-------+-------+
|  d2   |       |  d3   |   20
+-------+-------+-------+
|  d4   |       |  d5   |   21
+-------+-------+-------+
|  gnd  |       |  gnd  |   22
+-------+-------+-------+
|  d6   |       |  d7   |   23
+-------+-------+-------+
| _strt |       | _end  |   24
+-------+-------+-------+
|  _we  |       | _ss16 |   25
+-------+-------+-------+
|  gnd  |       |  gnd  |   26
+-------+-------+-------+
| _res  |       |  _irq |   27
+-------+-------+-------+
|  _br  |       |  _bg  |   28
+-------+-------+-------+
|       |       |       |   29
+-------+-------+-------+
|  gnd  |       |  gnd  |   30
+-------+-------+-------+
|  Vcc  |       |  gnd  |   31
+-------+-------+-------+
|  Vcc  |       |  gnd  |   32
+-------+-------+-------+

===============================
Kestrel Local Bus Specification
===============================
        I D E A   D R A F T   2

Goals:

* Semi-synchronous design to simplify interfacing logic.
* One byte per bus clock cycle maximum throughput.
* Demultiplexed address bus for easy access by peripheral circuitry.
* 8-bit data bus for homebrewing simplicity.
* RDY support for wait-state generation if required.
* Full bus mastering capability.

Mission Statement
=================

The mission of the KLB is to help facilitate homebrew electrical
engineering for the Kestrel series of computers in particular, and for
65816-based and Terbium-based platforms in general.  Because the Kestrel
itself is a homebrew computer, it is important that the bus architecture
not impose an extensive amount of financial burden on the builder.
Additionally, should the builder decide to create new peripherals that
require the KLB's high bandwidth, it should be easy and inexpensive for
someone to do so.  Dedicated bus bridges or specialized interface chips
should not be a requirement for someone to build a KLB peripheral --
standard 74HC(T) or 74AC(T) CMOS logic must suffice.

NOTE: The KLB is NOT a replacement for the alternative forms of
interconnects such as SS-22!  Whenever possible one should try to use
those.  The KLB is best used when adding more peripherals that need to be
accessed by the microprocessor or for those peripherals that draw or
deposit directly to/from system RAM.

The KLB is designed to present as close an interface to a 65816 as is
reasonable.  Therefore, we will not be repeating much of the 65816's bus
cycle description here, as it is already documented in readily available
materials from Western Design Center, Inc.

Note that the full KLB implementation uses two inline 2x20 pin female
headers on the motherboard for each slot.  J1 is the slave-only
interface, which a peripheral may use if it does not desire access to the
full address bus and has no bus mastering capability of its own.

More sophisticated expansion peripherals, it will make use of both J1 and
J2, the latter of which defines the remainder of the bus signals that are
of most use to a bus master, or a slave which requires access to the full
address bus (e.g., a RAM expansion card).

Pin-out: J1 (Slave-only Interface)
==================================

A01 : _VP       B01 : _RESET
A02 : RDY       B02 : VDA
A03 : SLOT0     B03 : n.c.
A04 : _IRQ      B04 : BUSCLK
A05 : SLOT1     B05 : _SLOTSEL
A06 : SLOT2     B06 : SLOT3
A07 : VPA       B07 : R_W
A08 : A0        B08 : D0
A09 : A1        B09 : D1
A10 : +Vdd      B10 : D2
A11 : GND       B11 : D3
A12 : A2        B12 : D4
A13 : A3        B13 : D5
A14 : A4        B14 : D6
A15 : A5        B15 : D7
A16 : A6        B16 : A15
A17 : A7        B17 : A14
A18 : A8        B18 : A13
A19 : A9        B19 : A12
A20 : A10       B20 : A11

The slave-only J1 header mimics a DIP 6502 microprocessor's pinout
closely.  There are some differences, however.

* +Vdd and GND are adjacent, to make decoupling easier for higher-speed
  operation.

* Many signals that would only be of interest to a bus master are moved
  to the J2 connector.  In their place are four pins to identify which
  slot the peripheral is plugged into, and a _SLOTSEL which is asserted
  whenever another bus master is accessing this peripherals local 64K I/O
  space ($Fs0000-$FsFFFF, where s is the slot number indicated by
  SLOT(0:3)).

* There is no NMI interrupt; peripherals only have access to an IRQ pin.
  The IRQ pin is always affirmatively driven by the peripheral -- it is
  NOT open-drain.

Although the peripheral lacks direct access to A16-A23, it can deduce the
state of those address lines whenever _SLOTSEL is asserted.  By
definition of the Kestrel Local Bus specification, all slot space
occupies memory between $F00000-$FFFFFF, where the 2nd most-significant
nybble indicates the specific slot in question (e.g., slot 0 is at
$F00000-$F0FFFF, slot 1 at $F10000-$F1FFFF, etc).  In case a peripheral
needs to know its base address for any reason, the SLOT(0:3) signals are
provided to deliver this information.

Pins marked "n.c." are expressly reserved for future definition.

Pinout: J2 (Full Bus Extensions)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

C01 : A16       D01 : n.c.
C02 : A17       D02 : n.c.
C03 : A18       D03 : n.c.
C04 : A19       D04 : n.c.
C05 : A20       D05 : n.c.
C06 : A21       D06 : n.c.
C07 : A22       D07 : n.c.
C08 : A23       D08 : n.c.
C09 : _ML       D09 : n.c.
C10 : +Vdd      D10 : n.c.
C11 : GND       D11 : n.c.
C12 : _ABORT    D12 : n.c.
C13 : _BR       D13 : n.c.
C14 : _BG       D14 : n.c.
C15 : n.c.      D15 : n.c.
C16 : n.c.      D16 : n.c.
C17 : n.c.      D17 : n.c.
C18 : n.c.      D18 : n.c.
C19 : n.c.      D19 : n.c.
C20 : n.c.      D20 : n.c.

This header defines the remainder of the address bus, as well as some CPU
status signals that would be of use to a potential bus master.  In
addition, the slot-local bus arbitration handshaking signals _BR (bus
request) and _BG (bus grant) are defined here as well.

Of particular interest is the _ABORT pin.  This is often used for
implementing external MMU functionality.  It is not possible to implement
a complete, address-translating MMU with the current KLB specification.
However, it is possible to add memory *protection* as a separate adapter
card.


NOTE: _ABORT is positively driven, just like _IRQ is.  It is NOT an
      open-drain output.

Pins marked "n.c." are expressly reserved for future definition.

A00 : SLOT0     B00 : SLOT1
A01 : SLOT2     B01 : SLOT3
A02 : _RESET    B02 : _SLOTSEL
A03 : _VP       B03 : _IRQ
A04 : GND       B04 : GND
A05 : RDY_I     B05 : RDY_O
A06 : VPA       B06 : VDA
A07 : R_W       B07 : n.c.
A08 : _ML       B08 : BUSCLK
A09 : GND       B09 : GND
A10 : A0        B10 : A1
A11 : A2        B11 : A3
A12 : A4        B12 : A5
A13 : A6        B13 : A7
A14 : GND       B14 : GND
A15 : A8        B15 : A9
A16 : A10       B16 : A11
A17 : A12       B17 : A13
A18 : A14       B18 : A15
A19 : GND       B19 : GND
A20 : A16       B20 : A17
A21 : A18       B21 : A19
A22 : A20       B22 : A21
A23 : A22       B23 : A23
A24 : GND       B24 : GND
A25 : D0        B25 : D1
A26 : D2        B26 : D3
A27 : D4        B27 : D5
A28 : D6        B28 : D7
A29 : GND       B29 : GND
A30 : _ML       B30 : _ABORT
A31 : _BR       B31 : _BG
A32 : n.c.      B32 : n.c.
A33 : n.c.      B33 : n.c.
A34 : GND       B34 : GND
A35 : n.c.      B35 : n.c.
A36 : n.c.      B36 : n.c.
A37 : +5V       B37 : +5V
A38 : +5V       B38 : +5V
A39 : GND       B39 : GND